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Syst."],"published-print":{"date-parts":[[2015,11,24]]},"abstract":"<jats:p>It is common for large hardware designs to have a number of registers or memories whose contents have to be changed very seldom (e.g., only at startup). The conventional way of accessing these memories is through a low-speed memory bus. This bus uses valuable hardware resources, introduces long global connections, and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used. A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this article, we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus, the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.<\/jats:p>","DOI":"10.1145\/2700835","type":"journal-article","created":{"date-parts":[[2015,10,27]],"date-time":"2015-10-27T12:36:39Z","timestamp":1445949399000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip\u2019s Internal Configuration Infrastructure"],"prefix":"10.1145","volume":"9","author":[{"given":"Karel","family":"Heyse","sequence":"first","affiliation":[{"name":"Ghent University, ELIS Department, Gent, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jente","family":"Basteleus","sequence":"additional","affiliation":[{"name":"Ghent University, ELIS Department, Gent, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brahim Al","family":"Farisi","sequence":"additional","affiliation":[{"name":"Ghent University, ELIS Department, Gent, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[{"name":"Ghent University, ELIS Department, Gent, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Kadlcek","sequence":"additional","affiliation":[{"name":"Maxeler Technologies Ltd., London, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Pell","sequence":"additional","affiliation":[{"name":"Maxeler Technologies Ltd., London, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,10,27]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2010.77"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.17"},{"key":"e_1_2_1_3_1","volume-title":"Runtime reconfigurable routing. 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