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Syst."],"published-print":{"date-parts":[[2015,8,3]]},"abstract":"<jats:p>Recent advent of manycore system increases needs for larger but faster memory hierarchy. Emerging next generation memories such as on-chip DRAM and nonvolatile memory (NVRAM) are promising candidates for replacement of DRAM-only main memory. Combined with the manycore trends, it gives an opportunity to rethink conventional resource management system with a memory hierarchy for a single cloud node. In an attempt to mitigate the energy and memory problems, we propose MN-MATE, an elastic resource management architecture for a single cloud node with manycores, on-chip DRAM, and large size of off-chip DRAM and NVRAM. In MN-MATE, the hypervisor places consolidated VMs and balances memory among them. Based on the monitored information about the allocated memory, a guest OS co-schedules tasks accessing different types of memory with complementary access intensity. Polymorphic management of DRAM hierarchy accelerates average memory access speed inside each guest OS. A guest OS reduces energy consumption with small performance loss based on the NVRAM-aware data placement policy and the hybrid page cache. A new lightweight kernel is developed to reduce the overhead from the guest OS for scientific applications. Experiment results show that our techniques in MN-MATE platform improve system performance and reduce energy consumption.<\/jats:p>","DOI":"10.1145\/2701429","type":"journal-article","created":{"date-parts":[[2015,8,4]],"date-time":"2015-08-04T13:57:39Z","timestamp":1438696659000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["MN-MATE"],"prefix":"10.1145","volume":"12","author":[{"given":"Kyu Ho","family":"Park","sequence":"first","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]},{"given":"Woomin","family":"Hwang","sequence":"additional","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]},{"given":"Hyunchul","family":"Seok","sequence":"additional","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]},{"given":"Chulmin","family":"Kim","sequence":"additional","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]},{"given":"Dong-jae","family":"Shin","sequence":"additional","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]},{"given":"Dong Jin","family":"Kim","sequence":"additional","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]},{"given":"Min Kyu","family":"Maeng","sequence":"additional","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]},{"given":"Seong Min","family":"Kim","sequence":"additional","affiliation":[{"name":"Computer Engineering Research Laboratory, KAIST, Daejeon, South Korea"}]}],"member":"320","published-online":{"date-parts":[[2015,8,3]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"AMD. 2013. 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