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Syst."],"published-print":{"date-parts":[[2015,9,2]]},"abstract":"<jats:p>A low-swing clocking methodology is introduced to achieve low-power operation at 20nm FinFET technology. Low-swing clock trees are used in existing methodologies in order to decrease the dynamic power consumption in a trade-off for 3 issues: (1) the effect of leakage power consumption, which is becoming more dominant when the process scales sub-32nm; (2) the increase in insertion delay, resulting in a high clock skew; and (3) the difficulty in driving the existing DFF sinks with a low-swing clock signal without a timing violation. In this article, a FinFET-based low-swing clocking methodology is introduced to preserve the dynamic power savings of low-swing clocking while minimizing these three negative effects, facilitated through an efficient use of FinFET technology. At scaled performance constraints, the proposed methodology at 20nm FinFET leads to 42% total power savings (clock network+DFF) compared to a FinFET-based full-swing counterpart at the same frequency (3 GHz), thanks to the dynamic power savings of low-swing clocking and 3% power savings compared to a CMOS-based low-swing implementation running at the half frequency (1.5 GHz), thanks to the leakage power savings of FinFET technology.<\/jats:p>","DOI":"10.1145\/2701617","type":"journal-article","created":{"date-parts":[[2015,9,8]],"date-time":"2015-09-08T12:36:15Z","timestamp":1441715775000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["FinFET-Based Low-Swing Clocking"],"prefix":"10.1145","volume":"12","author":[{"given":"Can","family":"Sitik","sequence":"first","affiliation":[{"name":"Drexel University, Philadelphia, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emre","family":"Salman","sequence":"additional","affiliation":[{"name":"Stony Brook University, Stony Brook, NY"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leo","family":"Filippini","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung Jun","family":"Yoon","sequence":"additional","affiliation":[{"name":"Stony Brook University, College Station, TX"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Baris","family":"Taskin","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, PA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,9,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.826204"},{"volume-title":"Proceedings of the Symposium on VLSI Technology (VLSIT'12)","author":"Auth C.","key":"e_1_2_1_2_1","unstructured":"C. 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