{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T13:04:38Z","timestamp":1761311078604,"version":"3.41.0"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2015,9,21]],"date-time":"2015-09-21T00:00:00Z","timestamp":1442793600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["CCF-0915612"],"award-info":[{"award-number":["CCF-0915612"]}]},{"name":"Center for Hierarchical Manufacturing, UMass-Amherst"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2015,9,21]]},"abstract":"<jats:p>\n            Maintaining benefits of CMOS technology scaling is becoming challenging, primarily due to increased manufacturing complexities and unwanted passive power dissipations. This is particularly challenging in SRAM, where manufacturing precision and leakage power control are critical issues. To alleviate these challenges, we proposed a novel volatile memory alternative to SRAM called\n            <jats:italic>nanowire volatile RAM<\/jats:italic>\n            (NWRAM). Due to NWRAM's regular grid-based layout and innovative circuit style, manufacturing complexities are reduced and, at the same time, considerable benefits are attained in terms of performance and leakage power reduction. In this article we elaborate NWRAM's circuit aspects and manufacturability, and quantify benefits at 16nm technology node through simulation against state-of-the-art 6T-SRAM and gridded 8T-SRAM designs. Our results show that when lower bounds in design rules are considered, 10T-NWRAM's read and write time are 1.38x and 2x faster, and the leakage power is 14x better in comparison to high-performance 6T-SRAM. Similarly the 10T-NWRAM achieves 1.3x and 1.9x read and write performance, and 35x leakage power improvements compared to high-performance 8T-SRAM. 10T-NWRAM's density is comparable to 6T-SRAM and 8T-SRAM for lower bounds, but exhibits higher active power in similar comparisons. This article details all benchmarking results and provides thorough analysis of NWRAM's evaluations.\n          <\/jats:p>","DOI":"10.1145\/2714567","type":"journal-article","created":{"date-parts":[[2015,9,22]],"date-time":"2015-09-22T19:33:34Z","timestamp":1442950414000},"page":"1-13","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Nanowire Volatile RAM as an Alternative to SRAM"],"prefix":"10.1145","volume":"12","author":[{"given":"Mostafizur","family":"Rahman","sequence":"first","affiliation":[{"name":"University of Massachusetts Amherst, MA"}]},{"given":"Santosh","family":"Khasanvis","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, MA"}]},{"given":"Csaba Andras","family":"Moritz","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, MA"}]}],"member":"320","published-online":{"date-parts":[[2015,9,21]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1109\/IEDM.2004.1419253"},{"key":"e_1_2_1_2_1","first-page":"22","article-title":"Gridded design rule scaling: Taking the CPU toward the 16nm node","volume":"7274","author":"Bencher C.","year":"2009","journal-title":"Proc. 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