{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T18:21:48Z","timestamp":1776277308137,"version":"3.50.1"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,4,2]],"date-time":"2015-04-02T00:00:00Z","timestamp":1427932800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1219186"],"award-info":[{"award-number":["1219186"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2015,4,16]]},"abstract":"<jats:p>Modern microprocessor cores reach their high performance levels with the help of high clock rates, parallel and speculative execution of a large number of instructions, and vast cache hierarchies. Modern cores also have adaptive features to regulate power and temperature and avoid thermal emergencies. All of these features contribute to highly unpredictable execution times. In this article, we demonstrate that the execution time of in-order (IO), out-of-order (OoO), and OoO simultaneous multithreaded processors can be stable and predictable by stabilizing their mega instructions executed per second (MIPS) rate via a proportional, integral, and differential (PID) gain feedback controller and dynamic voltage and frequency scaling (DVFS).<\/jats:p>\n          <jats:p>Processor cores in idle cycles are continuously consuming power, which is highly undesirable in systems, especially in real-time systems. In addition to meeting deadlines in real-time systems, our MIPS rate stabilization framework can be applied on top of it to reduce power and energy by avoiding idle cycles. If processors are equipped with MIPS rate stabilization, the execution time can be predicted. Because the MIPS rate remains steady, a stabilized processor meets deadlines on time in real-time systems or in systems with quality-of-service execution latency requirements at the lowest possible frequency.<\/jats:p>\n          <jats:p>To demonstrate and evaluate this capability, we have selected a subset of the MiBench benchmarks with the widest execution rate variations. We stabilize their MIPS rate on a 1GHz Pentium III--like OoO single-thread microarchitecture, a 1.32GHz StrongARM-like IO microarchitecture, and the 1GHz OoO processor augmented with two-way and four-way simultaneous multithreading. Both IO and OoO cores can take advantage of the stabilization framework, but the energy per instruction of the stabilized OoO core is less because it runs at a lower frequency to meet the same deadlines.<\/jats:p>\n          <jats:p>The MIPS rate stabilization of complex processors using a PID feedback control loop is a general technique applicable to environments in which lower power or energy coupled with steady, predictable performance are desirable, although we target more specifically real-time systems in this article.<\/jats:p>","DOI":"10.1145\/2714575","type":"journal-article","created":{"date-parts":[[2015,4,3]],"date-time":"2015-04-03T20:29:44Z","timestamp":1428092984000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Dynamic MIPS Rate Stabilization for Complex Processors"],"prefix":"10.1145","volume":"12","author":[{"given":"Jinho","family":"Suh","sequence":"first","affiliation":[{"name":"University of Southern California, Los Angeles, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chieh-Ting","family":"Huang","sequence":"additional","affiliation":[{"name":"University of Southern California, Los Angeles, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michel","family":"Dubois","sequence":"additional","affiliation":[{"name":"University of Southern California, Los Angeles, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,4,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/1787770.1787789"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.845896"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45046-7"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086320"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.17"},{"key":"e_1_2_1_6_1","volume-title":"Proceedings of the Kool Chips 2000 Workshop.","author":"Childers Bruce","year":"2000","unstructured":"Bruce Childers , Hongliang Tang , and Rami Melhem . 2000 . Adapting processor supply voltage to instruction-level parallelism . In Proceedings of the Kool Chips 2000 Workshop. Bruce Childers, Hongliang Tang, and Rami Melhem. 2000. Adapting processor supply voltage to instruction-level parallelism. In Proceedings of the Kool Chips 2000 Workshop."},{"key":"e_1_2_1_7_1","volume-title":"Proceedings of the 2001 Symposium on VLSI Circuits.","author":"Clark Lawrence T.","year":"2001","unstructured":"Lawrence T. Clark . 2001 . Circuit design of XScale microprocessors . In Proceedings of the 2001 Symposium on VLSI Circuits. Lawrence T. Clark. 2001. Circuit design of XScale microprocessors. In Proceedings of the 2001 Symposium on VLSI Circuits."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1210268.1210272"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.18"},{"key":"e_1_2_1_10_1","first-page":"1","article-title":"Quantifying the impact of input data sets on program behavior and its applications","volume":"5","author":"Eeckhout Lieven","year":"2003","unstructured":"Lieven Eeckhout , Hans Vandierendonck , and Koen De Bosschere . 2003 . Quantifying the impact of input data sets on program behavior and its applications . Journal of Instruction-Level Parallelism 5 , 1, 1 -- 33 . Lieven Eeckhout, Hans Vandierendonck, and Koen De Bosschere. 2003. Quantifying the impact of input data sets on program behavior and its applications. Journal of Instruction-Level Parallelism 5, 1, 1--33.","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"e_1_2_1_11_1","volume-title":"Feedback Control of Dynamics Systems","author":"Franklin Gene F.","unstructured":"Gene F. Franklin , J. David Powell , and Abbas Emami-Naeini . 1986. Feedback Control of Dynamics Systems . Prentice Hall . Gene F. Franklin, J. David Powell, and Abbas Emami-Naeini. 1986. Feedback Control of Dynamics Systems. Prentice Hall."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_2_1_13_1","first-page":"1","article-title":"Simpoint 3.0: Faster and more flexible program phase analysis","volume":"7","author":"Hamerly Greg","year":"2005","unstructured":"Greg Hamerly , Erez Perelman , Jeremy Lau , and Brad Calder . 2005 . Simpoint 3.0: Faster and more flexible program phase analysis . Journal of Instruction Level Parallelism 7 , 4, 1 -- 28 . Greg Hamerly, Erez Perelman, Jeremy Lau, and Brad Calder. 2005. Simpoint 3.0: Faster and more flexible program phase analysis. Journal of Instruction Level Parallelism 7, 4, 1--28.","journal-title":"Journal of Instruction Level Parallelism"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343846"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379270"},{"key":"e_1_2_1_16_1","volume-title":"Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE","author":"Hughes Christopher J.","unstructured":"Christopher J. Hughes , Jayanth Srinivasan , and Sarita V. Adve . 2001b. Saving energy with architectural and frequency adaptations for multimedia applications . In Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE , Los Alamitos, CA, 250--261. Christopher J. Hughes, Jayanth Srinivasan, and Sarita V. Adve. 2001b. Saving energy with architectural and frequency adaptations for multimedia applications. In Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE, Los Alamitos, CA, 250--261."},{"key":"e_1_2_1_17_1","volume-title":"Intel Atom Processor Z5XX Series Datasheet","unstructured":"Intel. 2009. Intel Atom Processor Z5XX Series Datasheet . Intel Corporation . Intel. 2009. Intel Atom Processor Z5XX Series Datasheet. Intel Corporation."},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545233"},{"key":"e_1_2_1_19_1","volume-title":"Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS\u201902)","author":"Jain Rohit","unstructured":"Rohit Jain , Christopher J. Hughes , and Sarita V. Adve . 2002. Soft real-time scheduling on simultaneous multithreaded processors . In Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS\u201902) . IEEE, Los Alamitos, CA, 134--145. Rohit Jain, Christopher J. Hughes, and Sarita V. Adve. 2002. Soft real-time scheduling on simultaneous multithreaded processors. In Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS\u201902). IEEE, Los Alamitos, CA, 134--145."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241609"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1287624.1287702"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the USENIX Annual Technical Conference.","author":"Sueur Etienne Le","year":"2011","unstructured":"Etienne Le Sueur and Gernot Heiser . 2011 . Slow down or sleep, that is the question . In Proceedings of the USENIX Annual Technical Conference. Etienne Le Sueur and Gernot Heiser. 2011. Slow down or sleep, that is the question. In Proceedings of the USENIX Annual Technical Conference."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/645609.662954"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11950-7_2"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751887"},{"key":"e_1_2_1_27_1","volume-title":"Proceedings of the 2004 Symposium on VLSI Technology. IEEE","author":"Mistry K.","unstructured":"K. Mistry , M. Armstrong , C. Auth , S. Cea , T. Coan , T. Ghani , T. Hoffmann , A. Murthy , J. Sandford , R. Shaheed , K. Zawadzki , K. Zhang , S. Thompson , and M. Bohr . 2004. Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology . In Proceedings of the 2004 Symposium on VLSI Technology. IEEE , Los Alamitos, CA, 50--51. K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann, A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson, and M. Bohr. 2004. Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology. In Proceedings of the 2004 Symposium on VLSI Technology. IEEE, Los Alamitos, CA, 50--51."},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the 17th Euro Micro Conference on Real Time Systems (ECRTS\u201905)","author":"Ortego Pablo Montesinos","year":"2004","unstructured":"Pablo Montesinos Ortego and Paul Sack . 2004 . SESC: SuperESCalar simulator . In Proceedings of the 17th Euro Micro Conference on Real Time Systems (ECRTS\u201905) . 1--4. Pablo Montesinos Ortego and Paul Sack. 2004. SESC: SuperESCalar simulator. In Proceedings of the 17th Euro Micro Conference on Real Time Systems (ECRTS\u201905). 1--4."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/563998.564004"},{"key":"e_1_2_1_30_1","series-title":"Vol. 2","volume-title":"Version 6","author":"SAS Institute","unstructured":"SAS Institute . 1990. SAS\/ STAT User\u2019s Guide : Version 6 ( Vol. 2 ) . SAS Institute . SAS Institute. 1990. SAS\/STAT User\u2019s Guide: Version 6 (Vol. 2). SAS Institute."},{"key":"e_1_2_1_31_1","volume-title":"Performance. Retrieved","author":"Shen John Paul","year":"2006","unstructured":"John Paul Shen . 2006 . Lost in the Bermuda Triangle: Complexity vs. Energy vs . Performance. Retrieved January 22, 2015, from http:\/\/www.csl.cornell.edu\/&sim;albonesi\/wced06\/shen.pdf. John Paul Shen. 2006. Lost in the Bermuda Triangle: Complexity vs. Energy vs. Performance. Retrieved January 22, 2015, from http:\/\/www.csl.cornell.edu\/&sim;albonesi\/wced06\/shen.pdf."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/635506.605403"},{"key":"e_1_2_1_33_1","volume-title":"Proceedings of the 8th International Symposium on High-Performance Computer Architecture. IEEE","author":"Skadron Kevin","unstructured":"Kevin Skadron , Tarek Abdelzaher , and Mircea R. Stan . 2002. Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management . In Proceedings of the 8th International Symposium on High-Performance Computer Architecture. IEEE , Los Alamitos, CA, 17--28. Kevin Skadron, Tarek Abdelzaher, and Mircea R. Stan. 2002. Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture. IEEE, Los Alamitos, CA, 17--28."},{"key":"e_1_2_1_34_1","series-title":"Lecture Notes in Computer Science","volume-title":"Power-Aware Computer Systems","author":"Stanley-Marbell Phillip","unstructured":"Phillip Stanley-Marbell , Michael S. Hsiao , and Ulrich Kremer . 2003. A hardware architecture for dynamic performance and energy adaptation . In Power-Aware Computer Systems . Lecture Notes in Computer Science , Vol. 2325 . Springer , 33--52. Phillip Stanley-Marbell, Michael S. Hsiao, and Ulrich Kremer. 2003. A hardware architecture for dynamic performance and energy adaptation. In Power-Aware Computer Systems. Lecture Notes in Computer Science, Vol. 2325. Springer, 33--52."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555763"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1210268.1210275"},{"key":"e_1_2_1_37_1","volume-title":"Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE","author":"Dean","unstructured":"Dean M. Tullsen and Jeffery A. Brown. 2001. Handling long-latency loads in a simultaneous multithreading processor . In Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE , Los Alamitos, CA, 318--327. Dean M. Tullsen and Jeffery A. Brown. 2001. Handling long-latency loads in a simultaneous multithreading processor. In Proceedings of the 34th Annual ACM\/IEEE International Symposium on Microarchitecture. IEEE, Los Alamitos, CA, 318--327."},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/232974.232993"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/951710.951744"},{"key":"e_1_2_1_40_1","volume-title":"Proceedings of the 9th IASTED International Conference on Internet and Multimedia Systems and Applications.","author":"Xu Ce","year":"2005","unstructured":"Ce Xu , Thinh M. Le , and Teng-Tiow Tay . 2005 . H. 264\/AVC codec: Instruction level complexity analysis . In Proceedings of the 9th IASTED International Conference on Internet and Multimedia Systems and Applications. Ce Xu, Thinh M. Le, and Teng-Tiow Tay. 2005. H. 264\/AVC codec: Instruction level complexity analysis. In Proceedings of the 9th IASTED International Conference on Internet and Multimedia Systems and Applications."},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2007.28"},{"key":"e_1_2_1_42_1","volume-title":"Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS\u201904)","author":"Zhu Yifan","year":"2004","unstructured":"Yifan Zhu and Frank Mueller . 2004 . Feedback EDF scheduling exploiting dynamic voltage scaling . In Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS\u201904) . IEEE, Los Alamitos, CA, 84--93. Yifan Zhu and Frank Mueller. 2004. Feedback EDF scheduling exploiting dynamic voltage scaling. In Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS\u201904). IEEE, Los Alamitos, CA, 84--93."}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2714575","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2714575","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T18:56:14Z","timestamp":1750272974000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2714575"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,4,2]]},"references-count":42,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,4,16]]}},"alternative-id":["10.1145\/2714575"],"URL":"https:\/\/doi.org\/10.1145\/2714575","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,4,2]]},"assertion":[{"value":"2013-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2014-12-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-04-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}