{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:17:34Z","timestamp":1763468254902,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":49,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,2,7]],"date-time":"2015-02-07T00:00:00Z","timestamp":1423267200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1216604,1012127"],"award-info":[{"award-number":["1216604,1012127"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,2,7]]},"DOI":"10.1145\/2716282.2716283","type":"proceedings-article","created":{"date-parts":[[2015,2,3]],"date-time":"2015-02-03T13:43:17Z","timestamp":1422970997000},"page":"25-35","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":51,"title":["Adaptive GPU cache bypassing"],"prefix":"10.1145","author":[{"given":"Yingying","family":"Tian","sequence":"first","affiliation":[{"name":"Texas A&M University, USA"}]},{"given":"Sooraj","family":"Puthoor","sequence":"additional","affiliation":[{"name":"AMD Research, USA"}]},{"given":"Joseph L.","family":"Greathouse","sequence":"additional","affiliation":[{"name":"AMD Research, USA"}]},{"given":"Bradford M.","family":"Beckmann","sequence":"additional","affiliation":[{"name":"AMD Research, USA"}]},{"given":"Daniel A.","family":"Jim\u00e9nez","sequence":"additional","affiliation":[{"name":"Texas A&M University, USA"}]}],"member":"320","published-online":{"date-parts":[[2015,2,7]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Advanced Micro Devices Inc. AMD Graphics Cores Next (GCN) Architecture. http:\/\/www.amd.com\/ Documents\/GCN_Architecture_whitepaper.pdf Jun. 2012.  Advanced Micro Devices Inc. AMD Graphics Cores Next (GCN) Architecture. http:\/\/www.amd.com\/ Documents\/GCN_Architecture_whitepaper.pdf Jun. 2012."},{"key":"e_1_3_2_1_2_1","unstructured":"Advanced Micro Devices Inc. AMD Radeon TM HD 7900 Series Graphics Cards: 7970 7970 GHz 7950. http:\/\/www.amd.com\/en-us\/products\/graphics\/ desktop\/7000\/7900 Jan. 2015.  Advanced Micro Devices Inc. AMD Radeon TM HD 7900 Series Graphics Cards: 7970 7970 GHz 7950. http:\/\/www.amd.com\/en-us\/products\/graphics\/ desktop\/7000\/7900 Jan. 2015."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1023833.1023869"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_5_1","volume-title":"Proc. of the Int\u2019l Conf. on Computational Intelligence and Neurosciences","author":"Bohn C.-A.","year":"1998","unstructured":"C.-A. Bohn . Kohonen Feature Mapping through Graphics Hardware . In Proc. of the Int\u2019l Conf. on Computational Intelligence and Neurosciences , 1998 . C.-A. Bohn. Kohonen Feature Mapping through Graphics Hardware. In Proc. of the Int\u2019l Conf. on Computational Intelligence and Neurosciences, 1998."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2008.05.014"},{"key":"e_1_3_2_1_8_1","unstructured":"Chipworks Inc. Inside the ASUS AMD 7970 graphics card - TSMC 28nm! http:\/\/www.chipworks.com\/en\/technicalcompetitive-analysis\/resources\/blog\/insidethe-asus-amd-7970-graphics-card-tsmc-28-nm\/ Feb. 2012.  Chipworks Inc. Inside the ASUS AMD 7970 graphics card - TSMC 28nm! http:\/\/www.chipworks.com\/en\/technicalcompetitive-analysis\/resources\/blog\/insidethe-asus-amd-7970-graphics-card-tsmc-28-nm\/ Feb. 2012."},{"key":"e_1_3_2_1_9_1","unstructured":"Chipworks Inc. A Look at Sony\u2019s Playstation 4 Core Processor. http:\/\/www.chipworks.com\/en\/ technical-competitive-analysis\/resources\/blog\/ a-look-at-sonys-playstation-4-core-processor Nov. 2013.  Chipworks Inc. A Look at Sony\u2019s Playstation 4 Core Processor. http:\/\/www.chipworks.com\/en\/ technical-competitive-analysis\/resources\/blog\/ a-look-at-sonys-playstation-4-core-processor Nov. 2013."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2188286.2188341"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1101149.1101334"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.5555\/862896.881093"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.12"},{"key":"e_1_3_2_1_14_1","volume-title":"Deconstructing the Inefficacy of Global Cache Replacement Policies. In Workshop on Duplicating, Deconstructing, and Debunking (WDDD)","author":"Garde R. V.","year":"2008","unstructured":"R. V. Garde , S. Subramaniam , and G. H. Loh . Deconstructing the Inefficacy of Global Cache Replacement Policies. In Workshop on Duplicating, Deconstructing, and Debunking (WDDD) , 2008 . R. V. Garde, S. Subramaniam, and G. H. Loh. Deconstructing the Inefficacy of Global Cache Replacement Policies. In Workshop on Duplicating, Deconstructing, and Debunking (WDDD), 2008."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000075"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/224538.224622"},{"key":"e_1_3_2_1_17_1","volume-title":"The OpenCL Specification Version 2.0","author":"Howes L.","year":"2014","unstructured":"L. Howes and A. Munshi . The OpenCL Specification Version 2.0 , 2014 . https:\/\/www.khronos.org\/ registry\/cl\/specs\/opencl-2.0.pdf. L. Howes and A. Munshi. The OpenCL Specification Version 2.0, 2014. https:\/\/www.khronos.org\/ registry\/cl\/specs\/opencl-2.0.pdf."},{"key":"e_1_3_2_1_18_1","unstructured":"HSA Foundation. HSA Programmer\u2019s Reference Manual: HSAIL Virtual ISA and Programming Model Compiler Writer\u2019s Guide and Object Format (BRIG). http:\/\/www.hsafoundation.com\/?ddownload=4945 Jun. 2014.  HSA Foundation. HSA Programmer\u2019s Reference Manual: HSAIL Virtual ISA and Programming Model Compiler Writer\u2019s Guide and Object Format (BRIG). http:\/\/www.hsafoundation.com\/?ddownload=4945 Jun. 2014."},{"key":"e_1_3_2_1_19_1","volume-title":"Morgan Kaufmann","author":"Hwu W. W.","year":"2011","unstructured":"W. W. Hwu , editor. GPU Computing Gems Emerald Edition . Morgan Kaufmann , 2011 . W. W. Hwu, editor. GPU Computing Gems Emerald Edition. Morgan Kaufmann, 2011."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2003.1240592"},{"key":"e_1_3_2_1_22_1","volume-title":"MRPB: Memory Request Prioritization for Massively Parallel Processors. In Int\u2019l Symp. on High Performance Computer Architecture (HPCA)","author":"Jia W.","year":"2014","unstructured":"W. Jia , K. A. Shaw , and M. Martonosi . MRPB: Memory Request Prioritization for Massively Parallel Processors. In Int\u2019l Symp. on High Performance Computer Architecture (HPCA) , 2014 . W. Jia, K. A. Shaw, and M. Martonosi. MRPB: Memory Request Prioritization for Massively Parallel Processors. In Int\u2019l Symp. on High Performance Computer Architecture (HPCA), 2014."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.817393"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451118"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822123"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.70816"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1229428.1229477"},{"key":"e_1_3_2_1_29_1","volume-title":"Heterogeneous System Architecture: A Technical Review. Technical report","author":"Kyriazis G.","year":"2012","unstructured":"G. Kyriazis . Heterogeneous System Architecture: A Technical Review. Technical report , HSA Foundation , 2012 . G. Kyriazis. Heterogeneous System Architecture: A Technical Review. Technical report, HSA Foundation, 2012."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379259"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168947"},{"key":"e_1_3_2_1_32_1","volume-title":"Sep.","author":"Tahiti Die-Shot AMD","year":"2012","unstructured":"Leonidas. AMD R1000\/ Tahiti Die-Shot . http:\/\/www.3dcenter.org\/abbildung\/ amd-r1000tahiti-die-shot-markiert , Sep. 2012 . Leonidas. AMD R1000\/Tahiti Die-Shot. http:\/\/www.3dcenter.org\/abbildung\/ amd-r1000tahiti-die-shot-markiert, Sep. 2012."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250707"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771793"},{"key":"e_1_3_2_1_35_1","volume-title":"Proc. of the Int\u2019l Conf. on Parallel Architectures and Compilation Techniques (PACT)","author":"Mekkat V.","year":"2013","unstructured":"V. Mekkat , A. Holey , P.-C. Yew , and A. Zhai . Managing Shared Last-Level Cache in a Heterogeneous Multicore Processor . In Proc. of the Int\u2019l Conf. on Parallel Architectures and Compilation Techniques (PACT) , 2013 . V. Mekkat, A. Holey, P.-C. Yew, and A. Zhai. Managing Shared Last-Level Cache in a Heterogeneous Multicore Processor. In Proc. of the Int\u2019l Conf. on Parallel Architectures and Compilation Techniques (PACT), 2013."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/1365490.1365500"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.41"},{"key":"e_1_3_2_1_39_1","volume-title":"NVIDIA\u2019s Next Generation CUDA Compute Architecture: Fermi","author":"Nvidia Corp.","year":"2009","unstructured":"Nvidia Corp. NVIDIA\u2019s Next Generation CUDA Compute Architecture: Fermi , 2009 . Nvidia Corp. NVIDIA\u2019s Next Generation CUDA Compute Architecture: Fermi, 2009."},{"key":"e_1_3_2_1_40_1","volume-title":"NVIDIA\u2019s Next Generation CUDA Compute Architecture: Kepler GK110","author":"Nvidia Corp.","year":"2012","unstructured":"Nvidia Corp. NVIDIA\u2019s Next Generation CUDA Compute Architecture: Kepler GK110 . 2012 . Nvidia Corp. NVIDIA\u2019s Next Generation CUDA Compute Architecture: Kepler GK110. 2012."},{"key":"e_1_3_2_1_41_1","unstructured":"Nvidia Corp. CUDA C Programming Guide Version 6.5. http:\/\/docs.nvidia.com\/cuda\/pdf\/CUDA_C_ Programming_Guide.pdf Aug. 2014.  Nvidia Corp. CUDA C Programming Guide Version 6.5. http:\/\/docs.nvidia.com\/cuda\/pdf\/CUDA_C_ Programming_Guide.pdf Aug. 2014."},{"key":"e_1_3_2_1_42_1","unstructured":"Nvidia Corp. Tuning CUDA Applications for Kepler. http:\/\/docs.nvidia.com\/cuda\/kepler-tuningguide\/ Aug. 2014.  Nvidia Corp. Tuning CUDA Applications for Kepler. http:\/\/docs.nvidia.com\/cuda\/kepler-tuningguide\/ Aug. 2014."},{"key":"e_1_3_2_1_43_1","unstructured":"Nvidia Corp. Tuning CUDA Applications for Maxwell. http:\/\/docs.nvidia.com\/cuda\/maxwell-tuningguide\/ Aug. 2014.  Nvidia Corp. Tuning CUDA Applications for Maxwell. http:\/\/docs.nvidia.com\/cuda\/maxwell-tuningguide\/ Aug. 2014."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917757"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277941"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.5555\/225160.225177"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"e_1_3_2_1_49_1","volume-title":"Cache Replacement Policy Revisited. In Workshop on Duplicating, Deconstructing, and Debunking (WDDD)","author":"Zahran M.","year":"2007","unstructured":"M. Zahran . Cache Replacement Policy Revisited. In Workshop on Duplicating, Deconstructing, and Debunking (WDDD) , 2007 . M. Zahran. Cache Replacement Policy Revisited. In Workshop on Duplicating, Deconstructing, and Debunking (WDDD), 2007."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333752"}],"event":{"name":"GPGPU-8: General-purpose Processing with Graphics Processing Units 8","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"],"location":"San Francisco CA USA","acronym":"GPGPU-8"},"container-title":["Proceedings of the 8th Workshop on General Purpose Processing using GPUs"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2716282.2716283","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2716282.2716283","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:00:42Z","timestamp":1750230042000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2716282.2716283"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2,7]]},"references-count":49,"alternative-id":["10.1145\/2716282.2716283","10.1145\/2716282"],"URL":"https:\/\/doi.org\/10.1145\/2716282.2716283","relation":{},"subject":[],"published":{"date-parts":[[2015,2,7]]},"assertion":[{"value":"2015-02-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}