{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:17:47Z","timestamp":1750306667886,"version":"3.41.0"},"reference-count":42,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,8,3]],"date-time":"2015-08-03T00:00:00Z","timestamp":1438560000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"the Air Force Office of Scientific Research under the MURI","award":["FA9550-12-1-0038"],"award-info":[{"award-number":["FA9550-12-1-0038"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2015,8,3]]},"abstract":"<jats:p>Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual memristors, conventional fixed-pulse write schemes cannot guarantee reliable completion of the write operations and waste significant amount of energy.<\/jats:p>\n          <jats:p>We propose an adaptive write scheme that adaptively adjusts the write pulses to address such variations in memristive arrays, resulting in 7\u00d7--11\u00d7 average energy saving in our case studies. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free crossbars. This feature also helps shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.<\/jats:p>","DOI":"10.1145\/2717313","type":"journal-article","created":{"date-parts":[[2015,8,4]],"date-time":"2015-08-04T13:57:39Z","timestamp":1438696659000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory"],"prefix":"10.1145","volume":"12","author":[{"given":"Amirali","family":"Ghofrani","sequence":"first","affiliation":[{"name":"University of California, Santa Barbara"}]},{"given":"Miguel-angel","family":"lastras-monta\u00f1o","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara"}]},{"given":"Siddharth","family":"Gaba","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor"}]},{"given":"Melika","family":"Payvand","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara"}]},{"given":"Wei","family":"Lu","sequence":"additional","affiliation":[{"name":"University of Michigan, Ann Arbor"}]},{"given":"Luke","family":"Theogarajan","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara"}]},{"given":"Kwang-Ting","family":"Cheng","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara"}]}],"member":"320","published-online":{"date-parts":[[2015,8,3]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_1_1_1","DOI":"10.1088\/0957-4484\/23\/7\/075201"},{"doi-asserted-by":"publisher","key":"e_1_2_1_2_1","DOI":"10.1109\/ISSCC.2008.4523240"},{"volume-title":"Proceedings of the International Test Conference. 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