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Code Optim."],"published-print":{"date-parts":[[2015,4,16]]},"abstract":"<jats:p>The performance of an IC degrades over its lifetime, ultimately resulting in IC failure. In this article, we present a hardware attack (called MAGIC) to maliciously accelerate NBTI aging effects in cores. In this attack, we identify the input patterns that maliciously age the pipestages of a core. We then craft a program that generates these patterns at the inputs of the targeted pipestage. We demonstrate the MAGIC-based attack on the OpenSPARC processor. Executing this program dramatically accelerates the aging process and degrades the processor\u2019s performance by 10.92% in 1 month, bypassing existing aging mitigation and timing-error correction schemes. We also present two low-cost techniques to thwart the proposed attack.<\/jats:p>","DOI":"10.1145\/2724718","type":"journal-article","created":{"date-parts":[[2015,4,3]],"date-time":"2015-04-03T20:29:44Z","timestamp":1428092984000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["MAGIC"],"prefix":"10.1145","volume":"12","author":[{"given":"Naghmeh","family":"Karimi","sequence":"first","affiliation":[{"name":"New York University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Arun Karthik","family":"Kanuparthi","sequence":"additional","affiliation":[{"name":"Security Center of Excellence, Intel Corporation, Hillsboro, OR"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xueyang","family":"Wang","sequence":"additional","affiliation":[{"name":"New York University, Brooklyn, NY"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[{"name":"New York University Abu Dhabi, UAE"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ramesh","family":"Karri","sequence":"additional","affiliation":[{"name":"New York University, Brooklyn, NY"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2015,4,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/1331699.1331710"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366121"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.22"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2006.10.012"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320111"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320885"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874657"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2348839.2348849"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2089657"},{"key":"e_1_2_1_11_1","volume-title":"Proceedings of VLSI Test Symposium (VTS\u201914)","author":"Cha Soonyoung","unstructured":"Soonyoung Cha , Chang-Chih Chen , Taizhi Liu , and Linda S. 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