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On the other hand, independently, microarchitectural enhancements for reliability to detect and tolerate natural faults have also been proposed. A fault in these security enhancements due to alpha particles or aging might potentially pass off maliciously modified instructions as safe, rendering the security enhancements useless. Deliberate fault attacks by attackers can be launched to disable the security enhancements and then launch the well-known security attacks that would otherwise have been detected by these enhancements. We report an integrated microarchitecture support for security and reliability in multicore processors. Specifically, we add integrity checkers to protect the code running on the multiple cores in a multicore processor. We then adapt these checkers to check one another periodically to ensure reliable operation. These checkers naturally can check the other parts of the core. The average performance, power, and area costs for these security-reliability enhancements are 6.42%, 0.73%, and 0.53%, respectively.<\/jats:p>","DOI":"10.1145\/2738052","type":"journal-article","created":{"date-parts":[[2015,5,11]],"date-time":"2015-05-11T16:30:57Z","timestamp":1431361857000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Reliable Integrity Checking in Multicore Processors"],"prefix":"10.1145","volume":"12","author":[{"given":"Arun","family":"Kanuparthi","sequence":"first","affiliation":[{"name":"Security Center of Excellence, Intel Corporation, Hillsboro,OR"}]},{"given":"Ramesh","family":"Karri","sequence":"additional","affiliation":[{"name":"New York University, Brooklyn, NY"}]}],"member":"320","published-online":{"date-parts":[[2015,5,11]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of Design Automation and Test in Europe (DATE\u201907)","author":"Aaraj Najwa","unstructured":"Najwa Aaraj , Anand Raghunathan , Srivaths Ravi , and Niraj K. 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