{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:17:25Z","timestamp":1763468245535,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,5,20]],"date-time":"2015-05-20T00:00:00Z","timestamp":1432080000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"SRC, National Science Foundation","award":["CCF-1252500, CCF-1302693"],"award-info":[{"award-number":["CCF-1252500, CCF-1302693"]}]},{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550-13-1-0110"],"award-info":[{"award-number":["FA9550-13-1-0110"]}],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,5,20]]},"DOI":"10.1145\/2742060.2742067","type":"proceedings-article","created":{"date-parts":[[2015,5,19]],"date-time":"2015-05-19T13:49:03Z","timestamp":1432043343000},"page":"63-68","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures"],"prefix":"10.1145","author":[{"given":"Sai Vineel Reddy","family":"Chittamuru","sequence":"first","affiliation":[{"name":"Colorado State University, Fort Collins, CO, USA"}]},{"given":"Srinivas","family":"Desai","sequence":"additional","affiliation":[{"name":"Colorado State University, Fort Collins, CO, USA"}]},{"given":"Sudeep","family":"Pasricha","sequence":"additional","affiliation":[{"name":"Colorado State University, Fort Collins, CO, USA"}]}],"member":"320","published-online":{"date-parts":[[2015,5,20]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"IEEE","author":"Ho R.","year":"2001","unstructured":"R. Ho , future of wires,\" in Proc . IEEE , Apr 2001 . R. Ho, et al., \"The future of wires,\" in Proc. IEEE, Apr 2001."},{"key":"e_1_3_2_1_2_1","volume-title":"not wires,\" in DAC","author":"Dally W. J.","year":"2001","unstructured":"W. J. Dally , B. Towles , \"Route packets , not wires,\" in DAC , 2001 . W. J. Dally, B. Towles, \"Route packets, not wires,\" in DAC, 2001."},{"key":"e_1_3_2_1_3_1","volume-title":"Yokohama","author":"Bahirat S.","year":"2011","unstructured":"S. Bahirat : A Multi-Layer Hybrid Photonic NoC for 3D ICs,\" in ASPDAC , Yokohama , Japan , Jan 2011 . S. Bahirat et al., \"OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs,\" in ASPDAC, Yokohama, Japan, Jan 2011."},{"key":"e_1_3_2_1_4_1","volume-title":"Special Issue on Silicon Photonics","author":"Miller D. A. B.","year":"2009","unstructured":"D. A. B. Miller , \"Device requirements for optical interconnects to silicon chips,\" in IEEE , Special Issue on Silicon Photonics , 2009 . D. A. B. Miller, \"Device requirements for optical interconnects to silicon chips,\" in IEEE, Special Issue on Silicon Photonics, 2009."},{"volume-title":"12.5gbit\/s carrier-injection-based silicon micro-ring silicon modulators,\" in Optics Express","author":"Xu Q.","key":"e_1_3_2_1_5_1","unstructured":"Q. Xu , \" 12.5gbit\/s carrier-injection-based silicon micro-ring silicon modulators,\" in Optics Express , vol. 15 , no. 2, Jan. 2007. Q. Xu et al., \"12.5gbit\/s carrier-injection-based silicon micro-ring silicon modulators,\" in Optics Express, vol. 15, no. 2, Jan. 2007."},{"issue":"1","key":"e_1_3_2_1_6_1","first-page":"46","article-title":"Ge-on soi-detector\/si-cmos-amplifier receivers for high-performance optical communication applications","volume":"25","author":"Koester S. J.","year":"2007","unstructured":"S. J. Koester , \" Ge-on soi-detector\/si-cmos-amplifier receivers for high-performance optical communication applications ,\" in JLT , vol. 25 , no. 1 , pp. 46 -- 57 , Jan. 2007 . S. J. Koester et al., \"Ge-on soi-detector\/si-cmos-amplifier receivers for high-performance optical communication applications,\" in JLT, vol. 25, no. 1, pp. 46--57, Jan. 2007.","journal-title":"JLT"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.91"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.35"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555808"},{"key":"e_1_3_2_1_10_1","volume-title":"Channel sharing for an energy efficient nanophotonic crossbar,\" in HPCA","author":"Pan Y.","year":"2010","unstructured":"Y. Pan , J. Kim , G. Memik , \"Flexishare : Channel sharing for an energy efficient nanophotonic crossbar,\" in HPCA , 2010 . Y. Pan, J. Kim, G. Memik, \"Flexishare: Channel sharing for an energy efficient nanophotonic crossbar,\" in HPCA, 2010."},{"key":"e_1_3_2_1_11_1","unstructured":"C. Chen A. Joshi \"Runtime management of laser power in silicon-photonic multibus NoC architecture \" in IEEE JQE 2013.  C. Chen A. Joshi \"Runtime management of laser power in silicon-photonic multibus NoC architecture \" in IEEE JQE 2013."},{"key":"e_1_3_2_1_12_1","volume-title":"All-optical switching on a silicon chip\" in Optics Letters, 29:2867--2869","author":"Almeida V.","year":"2004","unstructured":"V. Almeida , \" All-optical switching on a silicon chip\" in Optics Letters, 29:2867--2869 , 2004 . V. Almeida et al., \"All-optical switching on a silicon chip\" in Optics Letters, 29:2867--2869, 2004."},{"key":"e_1_3_2_1_13_1","volume-title":"Low-power-consumption short-length and high-modulation-depth silicon electro-optic modulator\" in JLT","author":"Barrios C. A.","year":"2003","unstructured":"C. A. Barrios , , \" Low-power-consumption short-length and high-modulation-depth silicon electro-optic modulator\" in JLT , 2003 . C. A. Barrios, et al., \"Low-power-consumption short-length and high-modulation-depth silicon electro-optic modulator\" in JLT, 2003."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.30"},{"key":"e_1_3_2_1_15_1","first-page":"107","volume-title":"Workshop","author":"Psota J.","year":"2007","unstructured":"J. Psota : On-chip optical networks for multicore processors,\" Boston Area Archit . Workshop , pp. 107 -- 108 , Jan. 2007 . J. Psota et al., \"ATAC: On-chip optical networks for multicore processors,\" Boston Area Archit. Workshop, pp. 107--108, Jan. 2007."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555809"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736024"},{"key":"e_1_3_2_1_19_1","volume-title":"Express","author":"Zheng X.","year":"2011","unstructured":"X. Zheng hybrid integrated silicon photonic transmitter and receiver,\" in Opt . Express , Mar 2011 . X. Zheng et al., \"Ultra-efficient 10Gb\/s hybrid integrated silicon photonic transmitter and receiver,\" in Opt. Express, Mar 2011."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2008.20"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071460"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669152"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2602155"},{"key":"e_1_3_2_1_24_1","volume-title":"An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors,\" in ISQED","author":"Pimpalkhute T.","year":"2014","unstructured":"T. Pimpalkhute , \" An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors,\" in ISQED 2014 . T. Pimpalkhute et al., \"An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors,\" in ISQED 2014."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"}],"event":{"name":"GLSVLSI '15: Great Lakes Symposium on VLSI 2015","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Pittsburgh Pennsylvania USA","acronym":"GLSVLSI '15"},"container-title":["Proceedings of the 25th edition on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2742060.2742067","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2742060.2742067","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:12:38Z","timestamp":1750227158000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2742060.2742067"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5,20]]},"references-count":25,"alternative-id":["10.1145\/2742060.2742067","10.1145\/2742060"],"URL":"https:\/\/doi.org\/10.1145\/2742060.2742067","relation":{},"subject":[],"published":{"date-parts":[[2015,5,20]]},"assertion":[{"value":"2015-05-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}