{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:17:43Z","timestamp":1750306663352,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":11,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,5,20]],"date-time":"2015-05-20T00:00:00Z","timestamp":1432080000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1117982"],"award-info":[{"award-number":["CCF-1117982"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,5,20]]},"DOI":"10.1145\/2742060.2742100","type":"proceedings-article","created":{"date-parts":[[2015,5,19]],"date-time":"2015-05-19T13:49:03Z","timestamp":1432043343000},"page":"397-402","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Optimizing VMIN of ROM Arrays Without Loss of Noise Margin"],"prefix":"10.1145","author":[{"given":"Avijit","family":"Chakraborty","sequence":"first","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.M.H.","family":"Walker","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,5,20]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"crossref","unstructured":"Zorian Y. 2002. Embedded memory test and repair: infrastructure IP for SOC yield In IEEE Int\"l Test Conf. 340--349. doi: 10.1109\/TEST.2002.1041777.   Zorian Y. 2002. Embedded memory test and repair: infrastructure IP for SOC yield In IEEE Int\"l Test Conf. 340--349. doi: 10.1109\/TEST.2002.1041777.","DOI":"10.1109\/TEST.2002.1041777"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2008.4567275"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Valaee A. Al-Khalili A. J. 2011. SRAM read-assist scheme for high performance low power applications. In Int\"l SoC Design Conf. 179--182. doi: 10.1109\/ISOCC.2011.6138676.  Valaee A. Al-Khalili A. J. 2011. SRAM read-assist scheme for high performance low power applications. In Int\"l SoC Design Conf. 179--182. doi: 10.1109\/ISOCC.2011.6138676.","DOI":"10.1109\/ISOCC.2011.6138676"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892153"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"crossref","unstructured":"Abouzeid F. Clerc S. Pelloux-Prayer B. Roche P. 2013. 0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm. In IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf. 1--2. doi: 10.1109\/S3S.2013.6716578.  Abouzeid F. Clerc S. Pelloux-Prayer B. Roche P. 2013. 0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm. In IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf. 1--2. doi: 10.1109\/S3S.2013.6716578.","DOI":"10.1109\/S3S.2013.6716578"},{"key":"e_1_3_2_1_6_1","first-page":"611","article-title":"A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply. In IEEE Int","volume":"474","author":"Zhang K.","year":"2005","journal-title":"l Solid-State Circuits Conf."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2004.1362403"},{"volume-title":"5th Int\"l Conf. on ASIC. 494--497. doi: 10.1109\/ICASIC.2003.1277594.","author":"Lin Hu Zhibiao Shao","key":"e_1_3_2_1_8_1"},{"volume-title":"Low-power and high-speed ROM modules for ASIC applications","author":"Ching-Rong Chang Jinn-Shyan","key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","DOI":"10.1109\/4.953480"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2005.36"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"Chang M.-F. Wen K-A; Chiou L.Y. 2005. Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique. In ElectronicsLetters. 834--835. doi: 10.1049\/el:2005173.  Chang M.-F. Wen K-A; Chiou L.Y. 2005. Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique. In ElectronicsLetters. 834--835. doi: 10.1049\/el:2005173.","DOI":"10.1049\/el:20051738"}],"event":{"name":"GLSVLSI '15: Great Lakes Symposium on VLSI 2015","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEEE CASS"],"location":"Pittsburgh Pennsylvania USA","acronym":"GLSVLSI '15"},"container-title":["Proceedings of the 25th edition on Great Lakes Symposium on VLSI"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2742060.2742100","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2742060.2742100","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T07:00:32Z","timestamp":1750230032000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2742060.2742100"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5,20]]},"references-count":11,"alternative-id":["10.1145\/2742060.2742100","10.1145\/2742060"],"URL":"https:\/\/doi.org\/10.1145\/2742060.2742100","relation":{},"subject":[],"published":{"date-parts":[[2015,5,20]]},"assertion":[{"value":"2015-05-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}