{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:16:32Z","timestamp":1750306592512,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,5,6]],"date-time":"2015-05-06T00:00:00Z","timestamp":1430870400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"High Tech. R&D Program of China","award":["2013AA01A215"],"award-info":[{"award-number":["2013AA01A215"]}]},{"name":"Brain Inspired Computing Research of Tsinghua University","award":["20141080934"],"award-info":[{"award-number":["20141080934"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,5,6]]},"DOI":"10.1145\/2742854.2742866","type":"proceedings-article","created":{"date-parts":[[2015,5,11]],"date-time":"2015-05-11T16:31:04Z","timestamp":1431361864000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Position-aware thread-level speculative parallelization for large-scale chip-multiprocessor"],"prefix":"10.1145","author":[{"given":"Li","family":"Yanhua","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhang","family":"Youhui","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China and Yangtze Delta Region Institute of Tsinghua University, ZheJiang, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zheng","family":"Weimin","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China and Yangtze Delta Region Institute of Tsinghua University, ZheJiang, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,5,6]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"226","volume-title":"A dynamic multithreading processor","author":"Akkary H.","year":"1998","unstructured":"H. Akkary and M. A. Driscoll . A dynamic multithreading processor . pages 226 -- 236 , 1998 . H. Akkary and M. A. Driscoll. A dynamic multithreading processor. pages 226--236, 1998."},{"key":"e_1_3_2_1_2_1","article-title":"An openmp extension that supports thread-level speculation. Parallel and Distributed Systems","author":"Aldea S.","year":"2015","unstructured":"S. Aldea , A. Estebanez , D. Llanos , and A. Gonzalez-Escribano . An openmp extension that supports thread-level speculation. Parallel and Distributed Systems , IEEE Transactions on, PP(99): 1--1 , 2015 . S. Aldea, A. Estebanez, D. Llanos, and A. Gonzalez-Escribano. An openmp extension that supports thread-level speculation. Parallel and Distributed Systems, IEEE Transactions on, PP(99): 1--1, 2015.","journal-title":"IEEE Transactions on, PP(99): 1--1"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.21"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.363382"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2011.21"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/EmbeddedCom-ScalCom.2009.128"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1898953.1898966"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/822079.822729"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155654"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261393"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1122971.1122997"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2541233"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/305138.305214"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1583991.1584050"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/248208.237151"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1108792.1108809"},{"key":"e_1_3_2_1_18_1","volume-title":"3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip","author":"Pierfrancesco Foglia F. P. M. S.","year":"2009","unstructured":"F. P. M. S. Pierfrancesco Foglia , Giacomo Gabrielli . Reducing sensitivity to noc latency in nuca caches . In 3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip , 2009 . F. P. M. S. Pierfrancesco Foglia, Giacomo Gabrielli. Reducing sensitivity to noc latency in nuca caches. In 3rd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, 2009."},{"key":"e_1_3_2_1_19_1","unstructured":"P. Sack. Sesc: Superescalar simulator. http:\/\/iacoma.cs.uiuc.edu\/paulsack\/sescdoc\/.  P. Sack. Sesc: Superescalar simulator. http:\/\/iacoma.cs.uiuc.edu\/paulsack\/sescdoc\/."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.5555\/874076.876480"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/1082469.1082471"},{"key":"e_1_3_2_1_22_1","volume-title":"In Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures in conjuction with ISCA-35","author":"Yoo R. M.","year":"2008","unstructured":"R. M. Yoo and H.-H. S. Lee . Helper transactions : Enabling thread-level speculation via a transactional memory system . In In Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures in conjuction with ISCA-35 , 2008 . R. M. Yoo and H.-H. S. Lee. Helper transactions: Enabling thread-level speculation via a transactional memory system. In In Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures in conjuction with ISCA-35, 2008."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.47"}],"event":{"name":"CF'15: Computing Frontiers Conference","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Ischia Italy","acronym":"CF'15"},"container-title":["Proceedings of the 12th ACM International Conference on Computing Frontiers"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2742854.2742866","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2742854.2742866","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:16:34Z","timestamp":1750227394000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2742854.2742866"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5,6]]},"references-count":23,"alternative-id":["10.1145\/2742854.2742866","10.1145\/2742854"],"URL":"https:\/\/doi.org\/10.1145\/2742854.2742866","relation":{},"subject":[],"published":{"date-parts":[[2015,5,6]]},"assertion":[{"value":"2015-05-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}