{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:16:32Z","timestamp":1750306592368,"version":"3.41.0"},"reference-count":19,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,12,2]],"date-time":"2015-12-02T00:00:00Z","timestamp":1449014400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1232164"],"award-info":[{"award-number":["1232164"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,12,2]]},"abstract":"<jats:p>Hierarchical and multi-network networks-on-chip (NoCs) have been proposed in the literature to improve the energy- and performance-efficient scalability of the traditional flat-mesh NoC architecture. Theoretically, based on a small-world network-based analysis, traditional hierarchical NoCs are expected to provide good scalability. However, the traditional theoretical analysis (e.g. for small-worldness) does not take into account the congestion phenomenon experienced in such networks. Counterintuitively, as shown in this work, breaking the hierarchy in traditional hierarchical NoCs and utilizing the proposed locality-aware network utilization (NU) balancing technique performs better. This improvement in performance is observed through experimental analysis, which is contrasted with the theoretical analysis that does not account for congestion. In addition to the novelties for hierarchical networks, the application of the proposed locality-aware NU balancing scheme is extended to multi-network NoC topologies (with already separated networks). Results of the analysis show the superiority of applying the locality-aware NU balancing technique for a throughput and energy-efficient scaling of the multi-network NoC architectures, much like those of the hierarchical NoCs. For instance, for a NoC with 1024 nodes, the proposed NU balancing technique provides up to 95% higher throughput efficiency and consumes up to 29% less energy per flit compared to the best NoC topology without the NU balancing technique. The analysis also helps to render the choice of a NoC topology for traffic patterns varying in locality and nonlocality on exascale computing CMPs.<\/jats:p>","DOI":"10.1145\/2743012","type":"journal-article","created":{"date-parts":[[2015,12,4]],"date-time":"2015-12-04T13:43:07Z","timestamp":1449236587000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Locality-Aware Network Utilization Balancing in NoCs"],"prefix":"10.1145","volume":"21","author":[{"given":"Ankit","family":"More","sequence":"first","affiliation":[{"name":"Drexel University, Philadelphia, PA"}]},{"given":"Baris","family":"Taskin","sequence":"additional","affiliation":[{"name":"Drexel University, Philadelphia, PA"}]}],"member":"320","published-online":{"date-parts":[[2015,12,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.0400087101"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1811100.1811103"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278667"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.3"},{"volume-title":"Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). 175--186","author":"Das R.","key":"e_1_2_1_6_1","unstructured":"R. Das , S. Eachempati , A. K. Mishra , V. Narayanan , and C. R. Das . 2009. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs . In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). 175--186 . R. Das, S. Eachempati, A. K. Mishra, V. Narayanan, and C. R. Das. 2009. Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). 175--186."},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1353610.1353628"},{"volume-title":"Proceedings of the Design, Automation Test in Europe (DATE). 423--428","author":"Kahng A. B.","key":"e_1_2_1_8_1","unstructured":"A. B. Kahng , B. Li , L. Peh , and K. Samadi . 2009. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration . In Proceedings of the Design, Automation Test in Europe (DATE). 423--428 . A. B. Kahng, B. Li, L. Peh, and K. Samadi. 2009. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In Proceedings of the Design, Automation Test in Europe (DATE). 423--428."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2633948.2633953"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.10"},{"key":"e_1_2_1_11_1","unstructured":"P. Kogge K. Bergman S. Borkar D. Campbell W. Carlson W. Dally M. Denneau P. Franzon W. Harrod K. Hill J. Hiller S. Karp S. Keckler D. Klein R. Lucas M. Richards A. Scarpelli S. Scott A. Snavely T. Sterling R. S. Williams and K. Yelick. 2008. ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems. DARPA.  P. Kogge K. Bergman S. Borkar D. Campbell W. Carlson W. Dally M. Denneau P. Franzon W. Harrod K. Hill J. Hiller S. Karp S. Keckler D. Klein R. Lucas M. Richards A. Scarpelli S. Scott A. Snavely T. Sterling R. S. Williams and K. Yelick. 2008. ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems. DARPA."},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2347655.2347671"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevE.75.027105"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MASCOTS.2006.9"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/AINAW.2007.131"},{"volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 105--116","author":"Wang H.","key":"e_1_2_1_18_1","unstructured":"H. Wang , L.-S. Peh , and S. Malik . 2003. Power-driven design of router microarchitectures in on-chip networks . In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 105--116 . H. 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In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 105--116."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837315"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2743012","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2743012","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2743012","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:16:34Z","timestamp":1750227394000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2743012"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12,2]]},"references-count":19,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,12,2]]}},"alternative-id":["10.1145\/2743012"],"URL":"https:\/\/doi.org\/10.1145\/2743012","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2015,12,2]]},"assertion":[{"value":"2013-01-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-12-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}