{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T11:48:34Z","timestamp":1763466514380,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,6,7]],"date-time":"2015-06-07T00:00:00Z","timestamp":1433635200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Huawei"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,6,7]]},"DOI":"10.1145\/2744769.2744871","type":"proceedings-article","created":{"date-parts":[[2015,6,2]],"date-time":"2015-06-02T05:35:02Z","timestamp":1433223302000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["Mitigating the impact of faults in unreliable memories for error-resilient applications"],"prefix":"10.1145","author":[{"given":"Shrikanth","family":"Ganapathy","sequence":"first","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgios","family":"Karakonstantis","sequence":"additional","affiliation":[{"name":"Queen's University Belfast, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adam","family":"Teman","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Burg","sequence":"additional","affiliation":[{"name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,6,7]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"ITRS - 2013 edition \" 2013. {Online}. Available: http:\/\/www.itrs.net  \"ITRS - 2013 edition \" 2013. {Online}. Available: http:\/\/www.itrs.net"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"volume-title":"Low-Power Variation-Tolerant Design in Nanometer Silicon","year":"2010","author":"Bhunia S.","key":"e_1_3_2_1_3_1"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2180407"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2223467"},{"volume-title":"Sparkk: Quality-scalable approximate storage in DRAM,\" in The Memory Forum","year":"2014","author":"Lucas J.","key":"e_1_3_2_1_6_1"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2596683"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540712"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.67"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228451"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-013-0736-4"},{"volume-title":"Robust importance sampling for efficient SRAM yield analysis,\" in ISQED","year":"2010","author":"Date T.","key":"e_1_3_2_1_13_1"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593184"},{"volume-title":"Shi-Ting et al., \"Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC,\" in ICCD","year":"2010","author":"Z.","key":"e_1_3_2_1_15_1"},{"volume-title":"13.8 a 32kb sram for error-free and error-tolerant applications with dynamic energy-quality management in 28nm cmos,\" in ISSCC","year":"2014","author":"Frustaci F.","key":"e_1_3_2_1_16_1"},{"volume-title":"Error correcting code analysis for cache memory high reliability and performance,\" in DATE","year":"2011","author":"Rossi D.","key":"e_1_3_2_1_17_1"},{"volume-title":"Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories,\" in DATE","year":"2015","author":"Teman A.","key":"e_1_3_2_1_18_1"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.dss.2009.05.016"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.patrec.2007.02.014"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00779-011-0415-z"},{"volume-title":"Learning Research","year":"2011","author":"Pedregosa F.","key":"e_1_3_2_1_22_1"}],"event":{"name":"DAC '15: The 52nd Annual Design Automation Conference 2015","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"San Francisco California","acronym":"DAC '15"},"container-title":["Proceedings of the 52nd Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2744769.2744871","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2744769.2744871","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:12:35Z","timestamp":1750227155000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2744769.2744871"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,7]]},"references-count":22,"alternative-id":["10.1145\/2744769.2744871","10.1145\/2744769"],"URL":"https:\/\/doi.org\/10.1145\/2744769.2744871","relation":{},"subject":[],"published":{"date-parts":[[2015,6,7]]},"assertion":[{"value":"2015-06-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}