{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T14:08:32Z","timestamp":1773410912357,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":41,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,6,7]],"date-time":"2015-06-07T00:00:00Z","timestamp":1433635200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,6,7]]},"DOI":"10.1145\/2744769.2753768","type":"proceedings-article","created":{"date-parts":[[2015,6,2]],"date-time":"2015-06-02T05:35:02Z","timestamp":1433223302000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Hybrid quick error detection (H-QED)"],"prefix":"10.1145","author":[{"given":"Keith A.","family":"Campbell","sequence":"first","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Lin","sequence":"additional","affiliation":[{"name":"Stanford University, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[{"name":"Stanford University, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Deming","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Illinois at Urbana-Champaign, Urbana, IL"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,6,7]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2008.77"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024916"},{"key":"e_1_3_2_1_3_1","unstructured":"{ARM CoreSight} ARM CoreSight http:\/\/www.arm.com\/products\/system-ip\/coresight.  {ARM CoreSight} ARM CoreSight http:\/\/www.arm.com\/products\/system-ip\/coresight."},{"key":"e_1_3_2_1_4_1","first-page":"196","article-title":"DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design","author":"T.","year":"1999","unstructured":"{Austin 99} Austin, T. M. , \" DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design ,\" Proc. IEEE\/ACM MICRO , pp. 196 -- 207 , 1999 . {Austin 99} Austin, T. M., \"DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design,\" Proc. IEEE\/ACM MICRO, pp. 196--207, 1999.","journal-title":"Proc. IEEE\/ACM MICRO"},{"key":"e_1_3_2_1_5_1","volume-title":"ISSCC","year":"2009","unstructured":"{Bohr 09} \"The New Era of Scaling in an SoC World,\" Proc . ISSCC 2009 . {Bohr 09} \"The New Era of Scaling in an SoC World,\" Proc. ISSCC 2009."},{"key":"e_1_3_2_1_6_1","unstructured":"{C11} International Organization for Standardization \"ISO\/IEC 9899:201x - Programming languages - C \" Dec 2011.  {C11} International Organization for Standardization \"ISO\/IEC 9899:201x - Programming languages - C \" Dec 2011."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147178"},{"key":"e_1_3_2_1_8_1","first-page":"1","article-title":"Effective Post-Silicon Failure Localization Using Dynamic Program Slicing","year":"2014","unstructured":"{Friedler 14} Friedler, O., , \" Effective Post-Silicon Failure Localization Using Dynamic Program Slicing ,\" DATE , pp. 1 -- 6 , 2014 . {Friedler 14} Friedler, O., et al., \"Effective Post-Silicon Failure Localization Using Dynamic Program Slicing,\" DATE, pp. 1--6, 2014.","journal-title":"DATE"},{"key":"e_1_3_2_1_9_1","first-page":"156","volume-title":"Proc. Intl. Solid State Circuits Conf.","author":"Fujigaya M.","year":"2013","unstructured":"{Fujigaya 13} M. Fujigaya , A 28nm High-&kappa; Netal-Gate Single-Chip Communications Processor with 1.5GHz Dual-Core Application Processor and LTE\/HSPA+-Capable Baseband Processor,\" Proc. Intl. Solid State Circuits Conf. , pp. 156 -- 157 , Feb. 2013 . {Fujigaya 13} M. Fujigaya, et al., \"A 28nm High-&kappa; Netal-Gate Single-Chip Communications Processor with 1.5GHz Dual-Core Application Processor and LTE\/HSPA+-Capable Baseband Processor,\" Proc. Intl. Solid State Circuits Conf., pp. 156--157, Feb. 2013."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1109118.1109121"},{"key":"e_1_3_2_1_11_1","first-page":"701","article-title":"On Error Modeling of Electrical Bugs for Post-silicon Timing Validation","author":"Gao M.","year":"2012","unstructured":"{Gao 12} M. Gao , , \" On Error Modeling of Electrical Bugs for Post-silicon Timing Validation ,\" ASPDAC , pp. 701 -- 706 , 2012 . {Gao 12} M. Gao, et al., \"On Error Modeling of Electrical Bugs for Post-silicon Timing Validation,\" ASPDAC, pp. 701--706, 2012.","journal-title":"ASPDAC"},{"key":"e_1_3_2_1_12_1","first-page":"87614","article-title":"Why Do Computers Stop and What Can Be Done About It?","volume":"7","author":"J.","year":"1985","unstructured":"{Gray 85} Gray, J. , \" Why Do Computers Stop and What Can Be Done About It? \" Tandem Computer, Tech. Report 85 . 7 , PN 87614 , 1985 . {Gray 85} Gray, J., \"Why Do Computers Stop and What Can Be Done About It?\" Tandem Computer, Tech. Report 85.7, PN 87614, 1985.","journal-title":"Tandem Computer, Tech. Report 85"},{"key":"e_1_3_2_1_13_1","volume-title":"Information Processing","author":"Hara Y.","year":"2009","unstructured":"{Hara 09} Y. Hara , Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis \", Information Processing , 2009 . {Hara 09} Y. Hara, et al., \"Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis\", Information Processing, 2009."},{"key":"e_1_3_2_1_14_1","volume-title":"Proc. Design Validation Conf.","author":"R. C.","year":"2009","unstructured":"{Ho 09} Ho, R. C. , et al., \"Post-Silicon Debug Using Formal Verification Waypoints,\" Proc. Design Validation Conf. , 2009 . {Ho 09} Ho, R. C., et al., \"Post-Silicon Debug Using Formal Verification Waypoints,\" Proc. Design Validation Conf., 2009."},{"key":"e_1_3_2_1_15_1","first-page":"1","volume-title":"IEE\/ACM Intl. Test Conf.","year":"2010","unstructured":"{Hong 10} Hong, T., : Quick Error Detection Tests for Effective Post-Silicon Validation,\" Proc . IEE\/ACM Intl. Test Conf. , pp. 1 -- 10 , 2010 . {Hong 10} Hong, T., et al., \"QED: Quick Error Detection Tests for Effective Post-Silicon Validation,\" Proc. IEE\/ACM Intl. Test Conf., pp. 1--10, 2010."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/157485.164963"},{"key":"e_1_3_2_1_17_1","first-page":"75","article-title":"LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation","author":"Lattner C.","year":"2004","unstructured":"{Lattner 04} C. Lattner and V. Adve , \" LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation ,\" CGO , pp. 75 -- 86 , 2004 . {Lattner 04} C. Lattner and V. Adve, \"LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation,\" CGO, pp. 75--86, 2004.","journal-title":"CGO"},{"key":"e_1_3_2_1_18_1","volume-title":"FOSDEM","author":"Clang C.","year":"2011","unstructured":"{Lattner 11} C. Lattner \"LLVM and Clang : Advancing Compiler Technology\", Keynote Talk , FOSDEM , 2011 . {Lattner 11} C. Lattner \"LLVM and Clang: Advancing Compiler Technology\", Keynote Talk, FOSDEM, 2011."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228461"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2334301"},{"key":"e_1_3_2_1_21_1","volume-title":"DATE","year":"2015","unstructured":"{Lin 15} Lin, D., , Quick Error Detection Tests with Fast Runtimes for Effective Post-Silicon Validation and Debug , DATE , 2015 . {Lin 15} Lin, D., et al., Quick Error Detection Tests with Fast Runtimes for Effective Post-Silicon Validation and Debug, DATE, 2015."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1676066"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.79"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.2145"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/832300.836638"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837280"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030595"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837367"},{"key":"e_1_3_2_1_30_1","unstructured":"{Pouchet 12} L. N. Pouchet. PolyBench\/C 3.2. http:\/\/www.cse.ohio-state.edu\/~pouchet\/software\/polybench\/  {Pouchet 12} L. N. Pouchet. PolyBench\/C 3.2. http:\/\/www.cse.ohio-state.edu\/~pouchet\/software\/polybench\/"},{"key":"e_1_3_2_1_31_1","volume-title":"DAC Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-Practices. DAC","year":"2012","unstructured":"{Reick 12} Reick, K., \"Post-Silicon Debug,\" DAC Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-Practices. DAC , 2012 . {Reick 12} Reick, K., \"Post-Silicon Debug,\" DAC Workshop on Post-Silicon Debug: Technologies, Methodologies, and Best-Practices. DAC, 2012."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2011.6157401"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/54.825675"},{"key":"e_1_3_2_1_34_1","first-page":"2172","volume-title":"c Proc","author":"McCluskey N. R.","year":"1998","unstructured":"{Saxena 98} Saxena, N. R. , and E. J. McCluskey , \"Dependable Adaptive Computing Systems , c Proc . IEEE Systems, Man , and Cybernetics Conf ., pp. 2172 -- 2177 , 1998 . {Saxena 98} Saxena, N. R., and E. J. McCluskey, \"Dependable Adaptive Computing Systems, c Proc. IEEE Systems, Man, and Cybernetics Conf., pp. 2172--2177, 1998."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024420"},{"key":"e_1_3_2_1_36_1","first-page":"184","volume-title":"Proc. IEEE VLSI Test Symp.","author":"E. S.","year":"2001","unstructured":"{Sogomonyan 01} Sogomoyan, E. S. , et al., \"Early Error Detection in System-on-Chip for Fault-Tolerance and At-Speed Debugging,\" Proc. IEEE VLSI Test Symp. , pp. 184 -- 189 , 2001 . {Sogomonyan 01} Sogomoyan, E. S., et al., \"Early Error Detection in System-on-Chip for Fault-Tolerance and At-Speed Debugging,\" Proc. IEEE VLSI Test Symp., pp. 184--189, 2001."},{"key":"e_1_3_2_1_37_1","volume-title":"Reversi: Post-Silicon Validation System for Modern Microprocessors,\" ICCD","author":"Bertacco V.","year":"2008","unstructured":"{Wagner 08} Wagner, I., and V. Bertacco , \" Reversi: Post-Silicon Validation System for Modern Microprocessors,\" ICCD 2008 . {Wagner 08} Wagner, I., and V. Bertacco, \"Reversi: Post-Silicon Validation System for Modern Microprocessors,\" ICCD 2008."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.898829"},{"key":"e_1_3_2_1_39_1","first-page":"344","volume-title":"Proc. IEEE\/ACM Asia and South Pacific Design Automation Conf.","year":"2004","unstructured":"{Wakabayashi 04} Wakabayashi, K., \"C-Based Behavioral Synthesis and Verification Analysis on Industrial Design Examples,\" Proc. IEEE\/ACM Asia and South Pacific Design Automation Conf. , pp. 344 -- 348 , 2004 . {Wakabayashi 04} Wakabayashi, K., \"C-Based Behavioral Synthesis and Verification Analysis on Industrial Design Examples,\" Proc. IEEE\/ACM Asia and South Pacific Design Automation Conf., pp. 344--348, 2004."},{"key":"e_1_3_2_1_40_1","first-page":"982","article-title":"Automated Data Analysis Solutions to Silicon Debug","author":"Yang Y.","year":"2009","unstructured":"{Yang 09} Y. Yang , N. Nicolici , and A. Veneris , \" Automated Data Analysis Solutions to Silicon Debug ,\" Proc. IEEE\/ACM Design Automation Test in Europe , pp. 982 -- 987 , 2009 . {Yang 09} Y. Yang, N. Nicolici, and A. Veneris, \"Automated Data Analysis Solutions to Silicon Debug,\" Proc. IEEE\/ACM Design Automation Test in Europe, pp. 982--987, 2009.","journal-title":"Proc. IEEE\/ACM Design Automation Test in Europe"},{"key":"e_1_3_2_1_41_1","volume-title":"ITC","year":"2006","unstructured":"{Yerramilli 06} Yerramilli, S., \"Addressing Post-Silicon Validation Challenges : Leverage Validation & Test Synergy,\" Keynote , ITC 2006 . {Yerramilli 06} Yerramilli, S., \"Addressing Post-Silicon Validation Challenges: Leverage Validation & Test Synergy,\" Keynote, ITC 2006."}],"event":{"name":"DAC '15: The 52nd Annual Design Automation Conference 2015","location":"San Francisco California","acronym":"DAC '15","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 52nd Annual Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2744769.2753768","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2744769.2753768","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:12:32Z","timestamp":1750227152000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2744769.2753768"}},"subtitle":["accelerator validation and debug using high-level synthesis principles"],"short-title":[],"issued":{"date-parts":[[2015,6,7]]},"references-count":41,"alternative-id":["10.1145\/2744769.2753768","10.1145\/2744769"],"URL":"https:\/\/doi.org\/10.1145\/2744769.2753768","relation":{},"subject":[],"published":{"date-parts":[[2015,6,7]]},"assertion":[{"value":"2015-06-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}