{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:46:46Z","timestamp":1772164006003,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,6,15]],"date-time":"2015-06-15T00:00:00Z","timestamp":1434326400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSF","award":["1213052"],"award-info":[{"award-number":["1213052"]}]},{"name":"NSF","award":["1205618"],"award-info":[{"award-number":["1205618"]}]},{"name":"NSF","award":["1017882"],"award-info":[{"award-number":["1017882"]}]},{"name":"NSF","award":["1439021"],"award-info":[{"award-number":["1439021"]}]},{"name":"NSF","award":["0963839"],"award-info":[{"award-number":["0963839"]}]},{"name":"Intel Inc."}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,6,15]]},"DOI":"10.1145\/2745844.2745867","type":"proceedings-article","created":{"date-parts":[[2015,6,8]],"date-time":"2015-06-08T11:11:12Z","timestamp":1433761872000},"page":"137-149","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":21,"title":["Memory Row Reuse Distance and its Role in Optimizing Application Performance"],"prefix":"10.1145","author":[{"given":"Mahmut","family":"Kandemir","sequence":"first","affiliation":[{"name":"The Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hui","family":"Zhao","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xulong","family":"Tang","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, University Park, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mustafa","family":"Karakoy","sequence":"additional","affiliation":[{"name":"TOBB ETU, Ankara, Turkey"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,6,15]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835945"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974655"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.34"},{"key":"e_1_3_2_1_5_1","volume-title":"ISCA","author":"Son S. O,Y. H.","year":"2014","unstructured":"S. O,Y. H. Son , N. S. Kim and J. H. Ahn , Row-buffer decoupling: a case for low-latency DRAM microarchitecture , ISCA , 2014 . S. O,Y. H. Son, N. S. Kim and J. H. Ahn, Row-buffer decoupling: a case for low-latency DRAM microarchitecture, ISCA, 2014."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1274971.1275005"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454145"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669176"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025127.1026001"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.22"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339668"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360134"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541962"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628096"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859653"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378661"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736045"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993744.1993748"},{"key":"e_1_3_2_1_20_1","volume-title":"HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , D. Han , O. Mutlu and M. Harchol-Balter , ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers , HPCA , 2010 . Y. Kim, D. Han, O. Mutlu and M. Harchol-Balter, ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers, HPCA, 2010."},{"key":"e_1_3_2_1_21_1","volume-title":"JESD79--3D edition","author":"JEDEC Solid State Technology Association","year":"2009","unstructured":"JEDEC Solid State Technology Association , DDR3 SDRAM Specification , JESD79--3D edition , Sept , 2009 JEDEC Solid State Technology Association, DDR3 SDRAM Specification, JESD79--3D edition, Sept, 2009"},{"key":"e_1_3_2_1_22_1","volume-title":"Technical report","year":"2007","unstructured":"Calculating Memory System Power for DDR3 , Technical report , Micron Technology Inc., 2--7, TN- 4-01, 2007 . Calculating Memory System Power for DDR3, Technical report, Micron Technology Inc., 2--7, TN-4-01, 2007."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.7"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/781131.781159"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601909"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"e_1_3_2_1_30_1","volume-title":"IPDCS","author":"Beyls K.","year":"2001","unstructured":"K. Beyls and E. H. D'Hollander , Reuse distance as a metric for cache behavior , IPDCS , 2001 . K. Beyls and E. H. D'Hollander, Reuse distance as a metric for cache behavior, IPDCS, 2001."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/773039.773043"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11970-5_15"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/360204.360219"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854286"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1854273.1854314"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451137"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611971538"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.5555\/647074.713908"},{"key":"e_1_3_2_1_40_1","unstructured":"https:\/\/www.nersc.gov\/users\/computational-systems\/cori\/nersc-8-procurement\/trinity-nersc-8-rfp\/nersc-8-trinity-benchmarks.  https:\/\/www.nersc.gov\/users\/computational-systems\/cori\/nersc-8-procurement\/trinity-nersc-8-rfp\/nersc-8-trinity-benchmarks."},{"key":"e_1_3_2_1_41_1","author":"Craik D J.","year":"1983","unstructured":"D J. Craik , A . Kumar , G. C. Levy , MOLDYN: a generalized program for the evaluation of molecular dynamics models using nuclear magnetic resonance spin-relaxation data , J. Chem. Inf. Comput. Sci. , 1983 . D J. Craik, A .Kumar, G. C. Levy, MOLDYN: a generalized program for the evaluation of molecular dynamics models using nuclear magnetic resonance spin-relaxation data, J. Chem. Inf. Comput. Sci., 1983.","journal-title":"J. Chem. Inf. Comput. Sci."},{"key":"e_1_3_2_1_42_1","unstructured":"https:\/\/software.sandia.gov\/hpcg\/html\/index.html.  https:\/\/software.sandia.gov\/hpcg\/html\/index.html."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605420"},{"key":"e_1_3_2_1_44_1","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy J.","year":"2012","unstructured":"J. Hennessy and D. Patterson , Computer Architecture: A Quantitative Approach , 4 th Edition, Morgan Kaufmann , 2012 . J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, 4th Edition, Morgan Kaufmann, 2012.","edition":"4"}],"event":{"name":"SIGMETRICS '15: ACM SIGMETRICS \/ International Conference on Measurement and Modeling of Computer Systems","location":"Portland Oregon USA","acronym":"SIGMETRICS '15","sponsor":["SIGMETRICS ACM Special Interest Group on Measurement and Evaluation"]},"container-title":["Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2745844.2745867","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2745844.2745867","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T02:16:43Z","timestamp":1750213003000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2745844.2745867"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,15]]},"references-count":43,"alternative-id":["10.1145\/2745844.2745867","10.1145\/2745844"],"URL":"https:\/\/doi.org\/10.1145\/2745844.2745867","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2796314.2745867","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2015,6,15]]},"assertion":[{"value":"2015-06-15","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}