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This leads to increasingly pessimistic design as technology scaling introduces increasingly significant parametric variations that result in an increasing performance variability. Alternatively, by allowing computations in a logic stage to complete in a variable number of clock cycles, variable-latency design provides relaxed timing constraints for average performance, area, and power consumption optimization. In this article, we present improved variable-latency design techniques including: (1) a generic minimum-intrusion variable-latency VLSI design paradigm, (2) a signal probability-based approximate prediction logic construction method for minimum misprediction rate at minimum cost, and (3) an application-specific cross-layer analysis methodology. Our experiments show that the proposed variable-latency design methodology on average reduces the computation latency by 26.80%(14.65%) at cost of 0.08%(3.4%) area and 0.4%(2.2%) energy consumption increase for the interger (floating point) unit of an open-source SPARC V8 processor LEON2 synthesized with a clock-cycle time between 1.97ns(3.49ns) and 5.96ns(13.74ns) based on the 45nm Nangate open cell library, while an automotive application-specific design further achieves an average latency reduction of 41.8%.<\/jats:p>","DOI":"10.1145\/2746341","type":"journal-article","created":{"date-parts":[[2015,9,22]],"date-time":"2015-09-22T12:31:00Z","timestamp":1442925060000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design"],"prefix":"10.1145","volume":"12","author":[{"given":"Vivek K.","family":"De","sequence":"first","affiliation":[{"name":"Intel Labs, Hillsboro, OR"}]},{"given":"Andrew B.","family":"Kahng","sequence":"additional","affiliation":[{"name":"University of California, San Diego, CA"}]},{"given":"Tanay","family":"Karnik","sequence":"additional","affiliation":[{"name":"Intel Labs, Hillsboro, OR"}]},{"given":"Bao","family":"Liu","sequence":"additional","affiliation":[{"name":"University of Texas at San Antonio, San Antonio, TX"}]},{"given":"Milad","family":"Maleki","sequence":"additional","affiliation":[{"name":"University of Texas at San Antonio, San Antonio, TX"}]},{"given":"Lu","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Texas at San Antonio, San Antonio, TX"}]}],"member":"320","published-online":{"date-parts":[[2015,9,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2008.07.039"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120878"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1274005"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.700720"},{"key":"e_1_2_1_5_1","unstructured":"L. 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