{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,29]],"date-time":"2026-09-29T16:59:20Z","timestamp":1790701160858,"version":"4.1.0"},"publisher-location":"New York, NY, USA","reference-count":63,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,6,13]],"date-time":"2015-06-13T00:00:00Z","timestamp":1434153600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["0953246,1065112,1212962,1320531"],"award-info":[{"award-number":["0953246,1065112,1212962,1320531"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2012R1A2A2A06047297"],"award-info":[{"award-number":["2012R1A2A2A06047297"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002994","name":"Ministry of Knowledge Economy","doi-asserted-by":"publisher","award":["10041608"],"award-info":[{"award-number":["10041608"]}],"id":[{"id":"10.13039\/501100002994","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,6,13]]},"DOI":"10.1145\/2749469.2750386","type":"proceedings-article","created":{"date-parts":[[2015,5,26]],"date-time":"2015-05-26T10:36:25Z","timestamp":1432636585000},"page":"105-117","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":584,"title":["A scalable processing-in-memory accelerator for parallel graph processing"],"prefix":"10.1145","author":[{"given":"Junwhan","family":"Ahn","sequence":"first","affiliation":[{"name":"Seoul National University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sungpack","family":"Hong","sequence":"additional","affiliation":[{"name":"Oracle Labs"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sungjoo","family":"Yoo","sequence":"additional","affiliation":[{"name":"Seoul National University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"Carnegie Mellon University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kiyoung","family":"Choi","sequence":"additional","affiliation":[{"name":"Seoul National University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2015,6,13]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ARM Cortex-A5 Processor. Available: http:\/\/www.arm.com\/products\/processors\/cortex-a\/cortex-a5.php  ARM Cortex-A5 Processor. Available: http:\/\/www.arm.com\/products\/processors\/cortex-a\/cortex-a5.php"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.55"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485943"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2080.357392"},{"key":"e_1_3_2_1_5_1","volume-title":"WWW","author":"Brin S.","year":"1998","unstructured":"S. Brin and L. Page , \" The anatomy of a large-scale hypertextual Web search engine,\" in Proc . WWW , 1998 . S. Brin and L. Page, \"The anatomy of a large-scale hypertextual Web search engine,\" in Proc. WWW, 1998."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.381947"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485945"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"key":"e_1_3_2_1_9_1","volume-title":"Thermal feasibility of die-stacked processing in memory,\" in WoNDP","author":"Eckert Y.","year":"2014","unstructured":"Y. Eckert , \" Thermal feasibility of die-stacked processing in memory,\" in WoNDP , 2014 . Y. Eckert et al., \"Thermal feasibility of die-stacked processing in memory,\" in WoNDP, 2014."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.375174"},{"key":"e_1_3_2_1_12_1","volume-title":"OSDI","author":"Gonzalez J. E.","year":"2012","unstructured":"J. E. Gonzalez : Distributed graph-parallel computation on natural graphs,\" in Proc . OSDI , 2012 . J. E. Gonzalez et al., \"PowerGraph: Distributed graph-parallel computation on natural graphs,\" in Proc. OSDI, 2012."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541951"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/331532.331589"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/1782174.1782200"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628071.2628091"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151013"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941590"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.14"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2581122.2544162"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2004.11.004"},{"key":"e_1_3_2_1_22_1","volume-title":"Tech. Rep.","year":"2013","unstructured":"\"Hybrid memory cube specification 1.0,\" Hybrid Memory Cube Consortium , Tech. Rep. , Jan. 2013 . \"Hybrid memory cube specification 1.0,\" Hybrid Memory Cube Consortium, Tech. Rep., Jan. 2013."},{"key":"e_1_3_2_1_23_1","volume-title":"Tech. Rep.","year":"2014","unstructured":"\"Hybrid memory cube specification 2.0,\" Hybrid Memory Cube Consortium , Tech. Rep. , Nov. 2014 . \"Hybrid memory cube specification 2.0,\" Hybrid Memory Cube Consortium, Tech. Rep., Nov. 2014."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242474"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/846215.846721"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1137\/S1064827595287997"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168873"},{"key":"e_1_3_2_1_29_1","volume-title":"PACT","author":"Kim G.","year":"2013","unstructured":"G. Kim system interconnect design with hybrid memory cubes,\" in Proc . PACT , 2013 . G. Kim et al., \"Memory-centric system interconnect design with hybrid memory cubes,\" in Proc. PACT, 2013."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540748"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.108"},{"key":"e_1_3_2_1_32_1","volume-title":"Proc. ISCA","author":"Kroft D.","year":"1981","unstructured":"D. Kroft , \"Lockup-free instruction fetch\/prefetch cache organization,\" in Proc. ISCA , 1981 . D. Kroft, \"Lockup-free instruction fetch\/prefetch cache organization,\" in Proc. ISCA, 1981."},{"key":"e_1_3_2_1_33_1","unstructured":"Laboratory for Web Algorithmics. Available: http:\/\/law.di.unimi.it\/datasets.php  Laboratory for Web Algorithmics. Available: http:\/\/law.di.unimi.it\/datasets.php"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485926"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"e_1_3_2_1_36_1","volume-title":"A processing-in-memory taxonomy and a case for studying fixed-function PIM,\" in WoNDP","author":"Loh G. H.","year":"2013","unstructured":"G. H. Loh , \" A processing-in-memory taxonomy and a case for studying fixed-function PIM,\" in WoNDP , 2013 . G. H. Loh et al., \"A processing-in-memory taxonomy and a case for studying fixed-function PIM,\" in WoNDP, 2013."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.14778\/2212351.2212354"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807167.1807184"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145816.2145832"},{"key":"e_1_3_2_1_41_1","volume-title":"Micron Technology","year":"2006","unstructured":"2Gb : x4, x8, x16 DDR3 SDRAM , Micron Technology , 2006 . 2Gb: x4, x8, x16 DDR3 SDRAM, Micron Technology, 2006."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1298306.1298311"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/822080.822823"},{"key":"e_1_3_2_1_44_1","unstructured":"Oracle TimesTen in-memory database. Available: http:\/\/www.oracle.com\/technetwork\/database\/timesten\/  Oracle TimesTen in-memory database. Available: http:\/\/www.oracle.com\/technetwork\/database\/timesten\/"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279387"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/1713254.1713276"},{"key":"e_1_3_2_1_47_1","volume-title":"Tech. Pap.","author":"Patterson D.","year":"1997","unstructured":"D. Patterson RAM (IRAM) : Chips that remember and compute,\" in ISSCC Dig . Tech. Pap. , 1997 . D. Patterson et al., \"Intelligent RAM (IRAM): Chips that remember and compute,\" in ISSCC Dig. Tech. Pap., 1997."},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485925"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2011.18"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2484838.2484843"},{"key":"e_1_3_2_1_52_1","unstructured":"SAP HANA. Available: http:\/\/www.saphana.com\/  SAP HANA. Available: http:\/\/www.saphana.com\/"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540726"},{"key":"e_1_3_2_1_55_1","volume-title":"ISCA","author":"Solihin Y.","year":"2002","unstructured":"Y. Solihin a user-level memory thread for correlation prefetching,\" in Proc . ISCA , 2002 . Y. Solihin et al., \"Using a user-level memory thread for correlation prefetching,\" in Proc. ISCA, 2002."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508274"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.14778\/2732232.2732238"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485944"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335248"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"e_1_3_2_1_62_1","volume-title":"A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing,\" in Proc. 3DIC","author":"Zhu Q.","year":"2013","unstructured":"Q. Zhu , \" A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing,\" in Proc. 3DIC , 2013 . Q. Zhu et al., \"A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing,\" in Proc. 3DIC, 2013."},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670336"}],"event":{"name":"ISCA '15: The 42nd Annual International Symposium on Computer Architecture","location":"Portland Oregon","acronym":"ISCA '15","sponsor":["IEEE TCCA IEEE Computer Society Technical Committee on Computer Architecture","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 42nd Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2749469.2750386","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2749469.2750386","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:00:40Z","timestamp":1750215640000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2749469.2750386"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,13]]},"references-count":63,"alternative-id":["10.1145\/2749469.2750386","10.1145\/2749469"],"URL":"https:\/\/doi.org\/10.1145\/2749469.2750386","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2872887.2750386","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2015,6,13]]},"assertion":[{"value":"2015-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}