{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T03:47:20Z","timestamp":1772164040355,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,6,13]],"date-time":"2015-06-13T00:00:00Z","timestamp":1434153600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,6,13]]},"DOI":"10.1145\/2749469.2750391","type":"proceedings-article","created":{"date-parts":[[2015,5,26]],"date-time":"2015-05-26T10:36:25Z","timestamp":1432636585000},"page":"311-322","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["SHRINK: Reducing the ISA complexity via instruction recycling"],"prefix":"10.1145","author":[{"given":"Bruno Cardoso","family":"Lopes","sequence":"first","affiliation":[{"name":"University of Campinas - UNICAMP - Brazil"}]},{"given":"Rafael","family":"Auler","sequence":"additional","affiliation":[{"name":"University of Campinas - UNICAMP - Brazil"}]},{"given":"Luiz","family":"Ramos","sequence":"additional","affiliation":[{"name":"University of Campinas - UNICAMP - Brazil"}]},{"given":"Edson","family":"Borin","sequence":"additional","affiliation":[{"name":"University of Campinas - UNICAMP - Brazil"}]},{"given":"Rodolfo","family":"Azevedo","sequence":"additional","affiliation":[{"name":"University of Campinas - UNICAMP - Brazil"}]}],"member":"320","published-online":{"date-parts":[[2015,6,13]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Nios II Processor Reference Handbook","year":"2011","unstructured":"Altera , Nios II Processor Reference Handbook , 2011 . Altera, Nios II Processor Reference Handbook, 2011."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485946"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.2002.1033225"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1053283.1053286"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522302"},{"key":"e_1_3_2_1_6_1","volume-title":"Dinero IV Trace-Driven Uniprocessor Cache Simulator","author":"Edler J.","year":"2003","unstructured":"J. Edler and M. Hill , \" Dinero IV Trace-Driven Uniprocessor Cache Simulator ,\" 2003 . J. Edler and M. Hill, \"Dinero IV Trace-Driven Uniprocessor Cache Simulator,\" 2003."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_8_1","volume-title":"AVX-512,\" http:\/\/www.agner.org\/optimize\/blog\/read.php?i=288, accessed","author":"Fog A.","year":"2014","unstructured":"A. Fog , \"Future instruction set : AVX-512,\" http:\/\/www.agner.org\/optimize\/blog\/read.php?i=288, accessed May 2014 . A. Fog, \"Future instruction set: AVX-512,\" http:\/\/www.agner.org\/optimize\/blog\/read.php?i=288, accessed May 2014."},{"key":"e_1_3_2_1_9_1","volume-title":"Instructions for Objconv","author":"Fog A.","year":"2011","unstructured":"A. Fog , Instructions for Objconv , 2011 , version 2.11. A. Fog, Instructions for Objconv, 2011, version 2.11."},{"key":"e_1_3_2_1_10_1","volume-title":"AMD and VIA CPUs,\"","author":"Fog A.","year":"2014","unstructured":"A. Fog , \"Lists of Instruction Latencies , Throughputs and Micro-Operation Breakdowns for Intel , AMD and VIA CPUs,\" 2014 , www.agner.org\/optimize\/instruction_tables.pdf. A. Fog, \"Lists of Instruction Latencies, Throughputs and Micro-Operation Breakdowns for Intel, AMD and VIA CPUs,\" 2014, www.agner.org\/optimize\/instruction_tables.pdf."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1968502.1968509"},{"key":"e_1_3_2_1_12_1","article-title":"ARM's 64-Bit Makeover","author":"Halfhill T. R.","year":"2012","unstructured":"T. R. Halfhill , \" ARM's 64-Bit Makeover ,\" The Linley Group Newsletters , December 2012 . T. R. Halfhill, \"ARM's 64-Bit Makeover,\" The Linley Group Newsletters, December 2012.","journal-title":"The Linley Group Newsletters"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.387728"},{"key":"e_1_3_2_1_15_1","volume-title":"IBM","year":"2013","unstructured":"Power ISA, Version 2. 07 ed ., IBM , 2013 . Power ISA, Version 2.07 ed., IBM, 2013."},{"key":"e_1_3_2_1_16_1","volume-title":"Volume 2: Instruction Set Reference ed","unstructured":"IA-32 Intel Architecture Software Developer's Manual , Volume 2: Instruction Set Reference ed ., Intel Corporation . IA-32 Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference ed., Intel Corporation."},{"key":"e_1_3_2_1_17_1","volume-title":"NewFrontiers in Performance Improvements and Energy Efficiency","author":"Intel Corporation","year":"2008","unstructured":"Intel Corporation , \"Intel AVX : NewFrontiers in Performance Improvements and Energy Efficiency ,\" 2008 , white paper. Intel Corporation, \"Intel AVX: NewFrontiers in Performance Improvements and Energy Efficiency,\" 2008, white paper."},{"key":"e_1_3_2_1_18_1","volume-title":"accessed","author":"Intel Corporation","year":"2014","unstructured":"Intel Corporation , \"Haswell New Instruction Descriptions Now Available,\" http:\/\/software.intel.com\/en-us\/blogs\/2011\/06\/13\/haswell-new-instruction-descriptions-now-available, 2012 , accessed May 2014 . Intel Corporation, \"Haswell New Instruction Descriptions Now Available,\" http:\/\/software.intel.com\/en-us\/blogs\/2011\/06\/13\/haswell-new-instruction-descriptions-now-available, 2012, accessed May 2014."},{"key":"e_1_3_2_1_19_1","volume-title":"Fourteenth International Conference on","author":"Jain M.","year":"2001","unstructured":"M. Jain , M. Balakrishnan , and A. Kumar , \" ASIP Design Methodologies: Survey and Issues,\" in VLSI Design, 2001 . Fourteenth International Conference on , 2001 . M. Jain, M. Balakrishnan, and A. Kumar, \"ASIP Design Methodologies: Survey and Issues,\" in VLSI Design, 2001. Fourteenth International Conference on, 2001."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2009.06.002"},{"key":"e_1_3_2_1_21_1","volume-title":"http:\/\/www.realworldtech.com\/haswell-cpu\/2\/, accessed","author":"Kanter D.","year":"2014","unstructured":"D. Kanter , \"Intel's Haswell CPU Microarchitecture ,\" Real World Technologies, November 2012 , http:\/\/www.realworldtech.com\/haswell-cpu\/2\/, accessed May 2014 . D. Kanter, \"Intel's Haswell CPU Microarchitecture,\" Real World Technologies, November 2012, http:\/\/www.realworldtech.com\/haswell-cpu\/2\/, accessed May 2014."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/948109.948146"},{"key":"e_1_3_2_1_23_1","article-title":"Using SSE and SSE2: Misconceptions and Reality","author":"Kilmovitski A.","year":"2001","unstructured":"A. Kilmovitski , \" Using SSE and SSE2: Misconceptions and Reality ,\" Intel Developer Update Magazine , 2001 . A. Kilmovitski, \"Using SSE and SSE2: Misconceptions and Reality,\" Intel Developer Update Magazine, 2001.","journal-title":"Intel Developer Update Magazine"},{"issue":"29","key":"e_1_3_2_1_24_1","first-page":"1996","article-title":"Bochs: A Portable PC Emulator for Unix\/X","volume":"1996","author":"Lawton K. P.","unstructured":"K. P. Lawton , \" Bochs: A Portable PC Emulator for Unix\/X ,\" Linux J. , vol. 1996 , no. 29 es, Sep. 1996 . K. P. Lawton, \"Bochs: A Portable PC Emulator for Unix\/X,\" Linux J., vol. 1996, no. 29es, Sep. 1996.","journal-title":"Linux J."},{"key":"e_1_3_2_1_25_1","volume-title":"accesses","author":"Morgan T. P.","year":"2014","unstructured":"T. P. Morgan , \" AMD to Double up Cores With Jaguars And Maybe Finally a Cat Server Variant,\" http:\/\/www.theregister.co.uk\/2012\/08\/29\/amd_jaguar_core_design\/, 2012 , accesses May 2014 . T. P. Morgan, \"AMD to Double up Cores With Jaguars And Maybe Finally a Cat Server Variant,\" http:\/\/www.theregister.co.uk\/2012\/08\/29\/amd_jaguar_core_design\/, 2012, accesses May 2014."},{"key":"e_1_3_2_1_26_1","volume-title":"accessed","author":"Morgan T. P.","year":"2014","unstructured":"T. P. Morgan , \"Intel Plugs Both Your Sockets With 'Jaketown' Xeon E5-2600s,\" http:\/\/www.theregister.co.uk\/2012\/03\/06\/intel_xeon_2600_server_chip_launch\/, 2012 , accessed May 2014 . T. P. Morgan, \"Intel Plugs Both Your Sockets With 'Jaketown' Xeon E5-2600s,\" http:\/\/www.theregister.co.uk\/2012\/03\/06\/intel_xeon_2600_server_chip_launch\/, 2012, accessed May 2014."},{"key":"e_1_3_2_1_27_1","volume-title":"Modern Processor Design: Fundamentals of Superscalar Processors, ser. McGraw-Hill Series in Electrical and Computer Engineering","author":"Shen J.","year":"2004","unstructured":"J. Shen , Modern Processor Design: Fundamentals of Superscalar Processors, ser. McGraw-Hill Series in Electrical and Computer Engineering . McGraw-Hill Companies, Inc orporated, 2004 . J. Shen, Modern Processor Design: Fundamentals of Superscalar Processors, ser. McGraw-Hill Series in Electrical and Computer Engineering. McGraw-Hill Companies, Incorporated, 2004."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1124713.1124722"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2007.44"},{"key":"e_1_3_2_1_30_1","first-page":"121","volume-title":"ISCA '14","author":"Venkat A.","year":"2014","unstructured":"A. Venkat and D. M. Tullsen , \" Harnessing ISA Diversity: Design of a heterogeneous-ISA Chip Multiprocessor,\" in Proceeding of the 41st Annual International Symposium on Computer Architecuture, ser . ISCA '14 . Piscataway, NJ, USA: IEEE Press , 2014 , pp. 121 -- 132 . Available: http:\/\/dl.acm.org\/citation.cfm?id=2665671.2665692 A. Venkat and D. M. Tullsen, \"Harnessing ISA Diversity: Design of a heterogeneous-ISA Chip Multiprocessor,\" in Proceeding of the 41st Annual International Symposium on Computer Architecuture, ser. ISCA '14. Piscataway, NJ, USA: IEEE Press, 2014, pp. 121--132. Available: http:\/\/dl.acm.org\/citation.cfm?id=2665671.2665692"},{"key":"e_1_3_2_1_31_1","volume-title":"ICCD 2009. IEEE International Conference on","author":"Weaver V.","year":"2009","unstructured":"V. Weaver and S. McKee , \" Code density concerns for new architectures,\" in Computer Design, 2009 . ICCD 2009. IEEE International Conference on , Oct 2009 . V. Weaver and S. McKee, \"Code density concerns for new architectures,\" in Computer Design, 2009. ICCD 2009. IEEE International Conference on, Oct 2009."}],"event":{"name":"ISCA '15: The 42nd Annual International Symposium on Computer Architecture","location":"Portland Oregon","acronym":"ISCA '15","sponsor":["IEEE TCCA IEEE Computer Society Technical Committee on Computer Architecture","SIGARCH ACM Special Interest Group on Computer Architecture"]},"container-title":["Proceedings of the 42nd Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2749469.2750391","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2749469.2750391","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T03:00:40Z","timestamp":1750215640000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2749469.2750391"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,13]]},"references-count":31,"alternative-id":["10.1145\/2749469.2750391","10.1145\/2749469"],"URL":"https:\/\/doi.org\/10.1145\/2749469.2750391","relation":{"is-identical-to":[{"id-type":"doi","id":"10.1145\/2872887.2750391","asserted-by":"object"}]},"subject":[],"published":{"date-parts":[[2015,6,13]]},"assertion":[{"value":"2015-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}