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A. Tyagi, H.-C. Ng, and P. Mohapatra, \"Dynamic branch decoupled architecture,\" in Computer Design, 1999.(ICCD'99) International Conference on. IEEE, 1999, pp. 442--450."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1479992.1480022"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195549"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1016\/0165-6074(88)90006-3"},{"key":"e_1_3_2_1_44_1","first-page":"23","volume-title":"ISPASS 2007. IEEE International Symposium on","author":"Yourst M.","year":"2007","unstructured":"M. Yourst , \"Ptlsim : A cycle accurate full system x86-64 microarchitectural simulator,\" in Performance Analysis of Systems Software, 2007 . ISPASS 2007. IEEE International Symposium on , April 2007 , pp. 23 -- 34 . M. Yourst, \"Ptlsim: A cycle accurate full system x86-64 microarchitectural simulator,\" in Performance Analysis of Systems Software, 2007. ISPASS 2007. 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