{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:14:09Z","timestamp":1750306449768,"version":"3.41.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2015,9,28]],"date-time":"2015-09-28T00:00:00Z","timestamp":1443398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European Commission in the context of the FP7 FASTER project"},{"name":"Flemish Fund for Scientific Research","award":["Ph.D."],"award-info":[{"award-number":["Ph.D."]}]},{"name":"Agency for Innovation through Science and Technology in Flanders","award":["Ph.D."],"award-info":[{"award-number":["Ph.D."]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,9,28]]},"abstract":"<jats:p>Parameterised configurations are FPGA configuration bitstreams in which the bits are defined as functions of user-defined parameters. From a parameterised configuration, it is possible to quickly and efficiently derive specialised, regular configuration bitstreams by evaluating these functions. The specialised bitstreams have different properties and functionality depending on the chosen values of the parameters. The most important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation, a technique for optimising circuits at runtime using partial reconfiguration of the FPGA.<\/jats:p>\n          <jats:p>Generating and using parameterised configurations requires a new FPGA tool flow. In this article, we present a new technology mapping algorithm for parameterised designs, called TCONMAP, that can be used to produce parameterised configurations in which both the configuration of the logic blocks and routing is a function of the parameters. In our experiments, we demonstrate that in using TCONMAP, the depth and area of the mapped circuit is close to the minimal depth and area attainable. Both Dynamic Circuit Specialisation and fine-grained modular reconfiguration are extracted by TCONMAP from the HDL description of the design requiring only simple parameter annotations.<\/jats:p>","DOI":"10.1145\/2751558","type":"journal-article","created":{"date-parts":[[2015,9,29]],"date-time":"2015-09-29T19:22:29Z","timestamp":1443554549000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["TCONMAP"],"prefix":"10.1145","volume":"20","author":[{"given":"Karel","family":"Heyse","sequence":"first","affiliation":[{"name":"Ghent University, Gent, Belgium"}]},{"given":"Brahim","family":"Al Farisi","sequence":"additional","affiliation":[{"name":"Ghent University, Gent, Belgium"}]},{"given":"Karel","family":"Bruneel","sequence":"additional","affiliation":[{"name":"Ghent University, Gent, Belgium"}]},{"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[{"name":"Ghent University, Gent, Belgium"}]}],"member":"320","published-online":{"date-parts":[[2015,9,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2491477.2491479"},{"volume-title":"Design planning for partial reconfiguration","key":"e_1_2_1_2_1","unstructured":"Altera. 2013. Design planning for partial reconfiguration . Altera Corporation . Altera. 2013. Design planning for partial reconfiguration. Altera Corporation."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.154"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.17"},{"key":"e_1_2_1_5_1","volume-title":"ABC: A system for sequential synthesis and verification","author":"Berkeley Logic Synthesis and Verification Group","year":"2007","unstructured":"Berkeley Logic Synthesis and Verification Group . 2007 . ABC: A system for sequential synthesis and verification . http:\/\/www.eecs.berkeley.edu\/&sim;alanmi\/abc. Berkeley Logic Synthesis and Verification Group. 2007. ABC: A system for sequential synthesis and verification. http:\/\/www.eecs.berkeley.edu\/&sim;alanmi\/abc."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/362342.362367"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2003695.2003703"},{"key":"e_1_2_1_8_1","unstructured":"Buddy. 2014. Binary Decision Diagram Library. http:\/\/buddy.sourceforge.net\/.  Buddy. 2014. Binary Decision Diagram Library. http:\/\/buddy.sourceforge.net\/."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382677"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/716984"},{"volume-title":"The TLUT Tool Flow","author":"Ghent University","key":"e_1_2_1_14_1","unstructured":"Ghent University . 2012. The TLUT Tool Flow . Hardware and Embedded Systems Group, Computer Systems Lab, ELIS Department . https:\/\/github.com\/UGent-HES\/tlut_flow. Ghent University. 2012. The TLUT Tool Flow. Hardware and Embedded Systems Group, Computer Systems Lab, ELIS Department. https:\/\/github.com\/UGent-HES\/tlut_flow."},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339224"},{"key":"e_1_2_1_16_1","unstructured":"Karel Heyse Tom Davidson Karel Bruneel and Dirk Stroobandt. 2013a. (Virtual) coarse grained reconfigurable architecture for regular expression matching. Tech. Rep. http:\/\/users.elis.ugent.be\/&sim;kheyse\/tech_report\/vcgra_regex.  Karel Heyse Tom Davidson Karel Bruneel and Dirk Stroobandt. 2013a. (Virtual) coarse grained reconfigurable architecture for regular expression matching. Tech. Rep. http:\/\/users.elis.ugent.be\/&sim;kheyse\/tech_report\/vcgra_regex."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645516"},{"key":"e_1_2_1_18_1","first-page":"b2","article-title":"Java Binary Decision Diagram Library","volume":"1","author":"BDD.","year":"2013","unstructured":"Java BDD. 2013 . Java Binary Decision Diagram Library , Release 1 .0 b2 . http:\/\/javabdd.sourceforge.net. JavaBDD. 2013. Java Binary Decision Diagram Library, Release 1.0b2. http:\/\/javabdd.sourceforge.net.","journal-title":"Release"},{"volume-title":"Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL).","author":"Koch Dirk","key":"e_1_2_1_19_1","unstructured":"Dirk Koch , Christian Beckhoff , and Guy G. F. Lemieux . 2013. An efficient FPGA overlay for portable custom instruction set extensions . In Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL). Dirk Koch, Christian Beckhoff, and Guy G. F. Lemieux. 2013. An efficient FPGA overlay for portable custom instruction set extensions. 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Partial Reconfiguration User Guide Xilinx."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2751558","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2751558","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:43:07Z","timestamp":1750225387000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2751558"}},"subtitle":["Technology Mapping for Parameterised FPGA Configurations"],"short-title":[],"issued":{"date-parts":[[2015,9,28]]},"references-count":28,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2015,9,28]]}},"alternative-id":["10.1145\/2751558"],"URL":"https:\/\/doi.org\/10.1145\/2751558","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2015,9,28]]},"assertion":[{"value":"2014-10-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-03-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-09-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}