{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:18:11Z","timestamp":1763457491674,"version":"3.41.0"},"reference-count":51,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2015,9,21]],"date-time":"2015-09-21T00:00:00Z","timestamp":1442793600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["EU-FP7-612069-HARPA"],"award-info":[{"award-number":["EU-FP7-612069-HARPA"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2015,9,21]]},"abstract":"<jats:p>\n            <jats:italic>Networks-on-chip<\/jats:italic>\n            (NoCs) are a widely recognized viable interconnection paradigm to support the multi-core revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due to the cores, since the NoC contribution to the overall energy budget is relevant. To face both static and dynamic power while balancing NoC performance, different actuators have been exploited in literature, mainly\n            <jats:italic>dynamic voltage frequency scaling<\/jats:italic>\n            (DVFS) and power gating. Typically, simulation-based tools are employed to explore the huge design space by adopting simplified models of the components. As a consequence, the majority of state-of-the-art on NoC power-performance optimization do not accurately consider timing and power overheads of actuators, or (even worse) do not consider them at all, with the risk of overestimating the benefits of the proposed methodologies.\n          <\/jats:p>\n          <jats:p>\n            This article presents a simulation framework for power-performance analysis of multicore architectures with specific focus on the NoC. It integrates accurate power gating and DVFS models encompassing also their timing and power overheads. The value added of our proposal is manyfold: (i) DVFS and power gating actuators are modeled starting from SPICE-level simulations; (ii) such models have been integrated in the simulation environment; (iii) policy analysis support is plugged into the framework to enable assessment of different policies; (iv) a flexible GALS (\n            <jats:italic>globally asynchronous locally synchronous<\/jats:italic>\n            ) support is provided, covering both handshake and FIFO re-synchronization schemas. To demonstrate both the flexibility and extensibility of our proposal, two simple policies exploiting the modeled actuators are discussed in the article.\n          <\/jats:p>","DOI":"10.1145\/2751561","type":"journal-article","created":{"date-parts":[[2015,9,22]],"date-time":"2015-09-22T12:31:00Z","timestamp":1442925060000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators"],"prefix":"10.1145","volume":"12","author":[{"given":"Davide","family":"Zoni","sequence":"first","affiliation":[{"name":"Politecnico di Milano, Milano, Italy"}]},{"given":"William","family":"Fornaciari","sequence":"additional","affiliation":[{"name":"Politecnico di Milano, Milano, Italy"}]}],"member":"320","published-online":{"date-parts":[[2015,9,21]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.102"},{"volume-title":"Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'09)","author":"Agarwal N.","key":"e_1_2_1_2_1"},{"volume-title":"Proceedings of the 17th IEEE International Conference on Telecommunications (ICT'10)","author":"Alhussien A.","key":"e_1_2_1_3_1"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.6"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785553"},{"volume-title":"Proceedings of the 2nd ACM\/IEEE International Symposium on Networks-on-Chip (NOCS'08)","author":"Beigne E.","key":"e_1_2_1_6_1"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2006.16"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_9_1","doi-asserted-by":"crossref","unstructured":"L. Bolzani A. Calimera A. Macii E. Macii and M. Poncino. 2009. Enabling concurrent clock and power gating in an industrial design flow. InProceedings of the Design Automation and Test in Europe Conference and Exhibition (DATE'09). 334--339.   L. Bolzani A. Calimera A. Macii E. Macii and M. Poncino. 2009. Enabling concurrent clock and power gating in an industrial design flow. InProceedings of the Design Automation and Test in Europe Conference and Exhibition (DATE'09). 334--339.","DOI":"10.1109\/DATE.2009.5090684"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339657"},{"key":"e_1_2_1_11_1","doi-asserted-by":"crossref","unstructured":"J. C. Butcher. 2003. Numerical Methods for Ordinary Differential Equations. Wiley.  J. C. Butcher. 2003. Numerical Methods for Ordinary Differential Equations. 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