{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T00:04:55Z","timestamp":1780445095734,"version":"3.54.1"},"reference-count":26,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2016,9,28]],"date-time":"2016-09-28T00:00:00Z","timestamp":1475020800000},"content-version":"vor","delay-in-days":366,"URL":"http:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000015","name":"Department of Energy","doi-asserted-by":"publisher","award":["DE-SC0005026"],"award-info":[{"award-number":["DE-SC0005026"]}],"id":[{"id":"10.13039\/100000015","id-type":"DOI","asserted-by":"publisher"}]},{"name":"SRC","award":["NSF 1218867, 1213052"],"award-info":[{"award-number":["NSF 1218867, 1213052"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,9,28]]},"abstract":"<jats:p>\n                    Resistive random access memory (ReRAM) technology is an emerging candidate for next-generation nonvolatile memory (NVM) architecture due to its simple structure, low programming voltage, fast switching speed, high on\/off ratio, excellent scalability, good endurance, and great compatibility with silicon CMOS technology. The most attractive of the characteristics of ReRAM is its cross-point structure, which features a 4\n                    <jats:italic toggle=\"yes\">F<\/jats:italic>\n                    <jats:sup>2<\/jats:sup>\n                    cell size.\n                  <\/jats:p>\n                  <jats:p>In a cross-point structure, the existence of sneak current and resulting voltage loss due to the wire's resistance might cause read and write failures if not designed properly. In addition, a robust ReRAM design needs to deal with both soft and hard errors. In this article, we summarize mechanisms of both soft and hard errors of ReRAM cells and propose a unified model to characterize different failure behaviors. We quantitatively analyze the impact of cell failure types on the reliability of the cross-point array. We also propose an error-resilient architecture, which avoids unnecessary writes in the hard error detection unit. Assuming constant soft error rate, our approach can extend the lifetime of ReRAM up to 75% over a design without hard error detection and up to 12% over the design with a \u201cwrite-verify\u201d detection mechanism. Our approach yields greater significant lifetime improvement when considering postcycling retention degradation.<\/jats:p>","DOI":"10.1145\/2753759","type":"journal-article","created":{"date-parts":[[2015,9,29]],"date-time":"2015-09-29T15:22:29Z","timestamp":1443540149000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design"],"prefix":"10.1145","volume":"20","author":[{"given":"Cong","family":"Xu","sequence":"first","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dimin","family":"Niu","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor Inc., San Jose, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yang","family":"Zheng","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[{"name":"Pennsylvania State University, University Park, PA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2015,9,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131539"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2012.6165051"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2251857"},{"key":"e_1_2_1_5_1","volume-title":"Proceedings of the IEEE Electron Devices Meeting (IEDM).","author":"Chen Yang Yin","unstructured":"Yang Yin Chen, M. Komura, R. Degraeve, B. Govoreanu, L. Goux, A Fantini, N. Raghavan, S. Clima, Leqi Zhang, A. Belmonte, A. Redolfi, G. S. Kar, G. Groeseneken, D. J. Wouters, and M. Jurczak. 2013b. Improvement of data retention in HfO2\/Hf 1T1R RRAM cell under low operating current. In Proceedings of the IEEE Electron Devices Meeting (IEDM)."},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1950815.1950821"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736023"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/1870926.1870961"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177078"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2062187"},{"key":"e_1_2_1_11_1","unstructured":"J. D. McCalpin. 2014. STREAM Benchmark. http:\/\/www.cs.virginia.edu\/stream."},{"key":"e_1_2_1_12_1","unstructured":"Mentor Graphics. 2014. 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Design Compiler. http:\/\/www.synopsys.com\/Tools\/Implementation\/RTLSynthesis\/Design Compiler."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228407"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/2561828.2561830"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"e_1_2_1_24_1","volume-title":"IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). 210--211","author":"Liu Tz","year":"2013","unstructured":"Tz yi Liu, Tian Hong Yan, R. Scheuerlein, Yingchang Chen, J. K. Lee, G. Balakrishnan, G. Yee, H. Zhang, A. Yap, J. Ouyang, T. Sasaki, S. Addepalli, A. Al-Shamma, Chin-Yu Chen, M. Gupta, et al. 2013. A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology. 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