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Such an architecture faces two main problems: how to efficiently control each processing element (PE) in the system, and how to facilitate inter-PE communication without the overheads of traditional shared-memory coherent memory. In this article, we explore solving these problems using triggered instructions and latency-insensitive channels. Triggered instructions completely eliminate the program counter (PC) and allow programs to transition concisely between states without explicit branch instructions. Latency-insensitive channels allow efficient communication of inter-PE control information while simultaneously enabling flexible code placement and improving tolerance for variable events such as cache accesses. Together, these approaches provide a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading.<\/jats:p>\n          <jats:p>Our analysis shows that a spatial accelerator using triggered instructions and latency-insensitive channels can achieve 8 \u00d7 greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64%, respectively, over a PC-style baseline, increasing the performance of the spatial programming approach by 2.0 \u00d7.<\/jats:p>","DOI":"10.1145\/2754930","type":"journal-article","created":{"date-parts":[[2015,9,15]],"date-time":"2015-09-15T12:09:15Z","timestamp":1442318955000},"page":"1-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures"],"prefix":"10.1145","volume":"33","author":[{"given":"Michael","family":"Pellauer","sequence":"first","affiliation":[{"name":"Intel, NVIDIA, Hudson, MA"}]},{"given":"Angshuman","family":"Parashar","sequence":"additional","affiliation":[{"name":"Intel, NVIDIA, Hudson, MA"}]},{"given":"Michael","family":"Adler","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Bushra","family":"Ahsan","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Randy","family":"Allmon","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Neal","family":"Crago","sequence":"additional","affiliation":[{"name":"Intel, NVIDIA, Hudson, MA"}]},{"given":"Kermin","family":"Fleming","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Mohit","family":"Gambhir","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Aamer","family":"Jaleel","sequence":"additional","affiliation":[{"name":"Intel, NVIDIA, Hudson, MA"}]},{"given":"Tushar","family":"Krishna","sequence":"additional","affiliation":[{"name":"Intel, Georgia Institute of Technology, Hudson, MA"}]},{"given":"Daniel","family":"Lustig","sequence":"additional","affiliation":[{"name":"Princeton University"}]},{"given":"Stephen","family":"Maresh","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Vladimir","family":"Pavlov","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Rachid","family":"Rayess","sequence":"additional","affiliation":[{"name":"Intel, Hudson, MA"}]},{"given":"Antonia","family":"Zhai","sequence":"additional","affiliation":[{"name":"University of Minnesota"}]},{"given":"Joel","family":"Emer","sequence":"additional","affiliation":[{"name":"Intel and MIT, NVIDIA, Hudson, MA"}]}],"member":"320","published-online":{"date-parts":[[2015,9,11]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.48862"},{"key":"e_1_2_1_2_1","volume-title":"Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. 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