{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:16:35Z","timestamp":1750306595540,"version":"3.41.0"},"reference-count":40,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,12,2]],"date-time":"2015-12-02T00:00:00Z","timestamp":1449014400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["CNS-1117425, CAREER-1253024, CCF-1318826, CNS-1421022, and CNS-1421068"],"award-info":[{"award-number":["CNS-1117425, CAREER-1253024, CCF-1318826, CNS-1421022, and CNS-1421068"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,12,2]]},"abstract":"<jats:p>\n            In this article, we demonstrate that the sensitized path delays in various microprocessor pipe stages exhibit intriguing temporal and spatial variations during the execution of real-world applications. To effectively exploit these delay variations, we propose\n            <jats:italic>dynamically adaptable resilient pipeline<\/jats:italic>\n            (DARP)\u2014a series of runtime techniques to boost power-performance efficiency and fault tolerance in a pipelined microprocessor. DARP employs early error prediction to avoid a major portion of the timing errors. We combine DARP with the state-of-art\n            <jats:italic>topologically homogeneous and power-performance heterogeneous<\/jats:italic>\n            (THPH) architecture to build up a new frontier for the energy efficiency of multicore processors (DARP-MP). Using a rigorous circuit-architectural infrastructure, we demonstrate that DARP substantially improves the multicore processor performance (9.4--20%) and energy efficiency (10--28.6%) compared to state-of-the-art techniques. The energy-efficiency improvements of DARP-MP are 42% and 49.9% compared against the original THPH and another state-of-art multicore power management scheme, respectively.\n          <\/jats:p>","DOI":"10.1145\/2755558","type":"journal-article","created":{"date-parts":[[2015,12,4]],"date-time":"2015-12-04T13:43:07Z","timestamp":1449236587000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["DARP-MP"],"prefix":"10.1145","volume":"21","author":[{"given":"Hu","family":"Chen","sequence":"first","affiliation":[{"name":"Utah State University, Logan, UT"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanghamitra","family":"Roy","sequence":"additional","affiliation":[{"name":"Utah State University, Logan, UT"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koushik","family":"Chakraborty","sequence":"additional","affiliation":[{"name":"Utah State University, Logan, UT"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,2]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629940"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007148"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629915"},{"volume-title":"Proceedings of the IEEE Custom Integrated Circuits Conference, (CICC'10)","author":"Chae K.","key":"e_1_2_1_5_1","unstructured":"K. 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