{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:15:39Z","timestamp":1750306539036,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":41,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,7,4]],"date-time":"2012-07-04T00:00:00Z","timestamp":1341360000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"French National Research Agency"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,7,4]]},"DOI":"10.1145\/2765491.2765495","type":"proceedings-article","created":{"date-parts":[[2015,4,22]],"date-time":"2015-04-22T15:50:56Z","timestamp":1429717856000},"page":"14-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Low-power design technique with ambipolar double gate devices"],"prefix":"10.1145","author":[{"given":"Kotb","family":"Jabeur","sequence":"first","affiliation":[{"name":"Lyon Institute of Nanotechnology -- Ecole Centrale de Lyon, Ecully, France"}]},{"given":"Ian","family":"O'Connor","sequence":"additional","affiliation":[{"name":"Lyon Institute of Nanotechnology -- Ecole Centrale de Lyon, Ecully, France"}]},{"given":"David","family":"Navarro","sequence":"additional","affiliation":[{"name":"Lyon Institute of Nanotechnology -- Ecole Centrale de Lyon, Ecully, France"}]},{"given":"S\u00e9bastien","family":"Le Beux","sequence":"additional","affiliation":[{"name":"Lyon Institute of Nanotechnology -- Ecole Centrale de Lyon, Ecully, France"}]}],"member":"320","published-online":{"date-parts":[[2012,7,4]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"56","article-title":"Effects of global Interconnect Optimizations on Performance Estimation of deep Submicron Design\" in IEEE\/ACM, (ICCAD2000), San Jose","author":"Cao Y.","year":"2000","unstructured":"Y. Cao and al , \" Effects of global Interconnect Optimizations on Performance Estimation of deep Submicron Design\" in IEEE\/ACM, (ICCAD2000), San Jose , CA, USA, 5-- 9 November 2000 ; pp. 56 -- 61 Y. Cao and al, \"Effects of global Interconnect Optimizations on Performance Estimation of deep Submicron Design\" in IEEE\/ACM, (ICCAD2000), San Jose, CA, USA, 5--9 November 2000; pp. 56--61","journal-title":"CA, USA, 5--"},{"key":"e_1_3_2_1_2_1","first-page":"143","volume-title":"RT-level Interconnect Optimization in DSM Regime\" in Proceedings of the IEEE Computer Society Workshop VLSI","author":"Katkoori S.","year":"2000","unstructured":"S. Katkoori and S. Alupoaei , \" RT-level Interconnect Optimization in DSM Regime\" in Proceedings of the IEEE Computer Society Workshop VLSI , 2000 , Orlando, FL , USA , 27--28 April 2000, pp. 143 -- 148 S. Katkoori and S. Alupoaei, \"RT-level Interconnect Optimization in DSM Regime\" in Proceedings of the IEEE Computer Society Workshop VLSI, 2000, Orlando, FL, USA, 27--28 April 2000, pp. 143--148"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/876896.880995"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/874057.875200"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147115"},{"key":"e_1_3_2_1_6_1","first-page":"55","article-title":"SRAM leakage suppression by minimizing standby supply voltage","author":"Qin H.","year":"2004","unstructured":"H. Qin and al , \" SRAM leakage suppression by minimizing standby supply voltage \" IEEE ISQED , pp. 55 -- 60 , 2004 . H. Qin and al, \"SRAM leakage suppression by minimizing standby supply voltage\" IEEE ISQED, pp. 55--60, 2004.","journal-title":"IEEE ISQED"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/988952.988991"},{"issue":"3","key":"e_1_3_2_1_8_1","article-title":"Multi-Purpose Technique to Decrease Leakage Power in VLSI Circuits","volume":"2","author":"Karimi G.","year":"2011","unstructured":"G. Karimi and al , \" Multi-Purpose Technique to Decrease Leakage Power in VLSI Circuits \", Canadian Journal on Electrical and Electronics Engineering Vol. 2 , No. 3 , March 2011 G. Karimi and al, \"Multi-Purpose Technique to Decrease Leakage Power in VLSI Circuits\", Canadian Journal on Electrical and Electronics Engineering Vol. 2, No. 3, March 2011","journal-title":"Canadian Journal on Electrical and Electronics Engineering"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.245594"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266182"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.871328"},{"key":"e_1_3_2_1_12_1","first-page":"53","volume-title":"Proc. CICC'96","author":"Kuroda T.","year":"1996","unstructured":"T. Kuroda and al, \" A High-speed Low-power 0.3 μm CMOS Gate Array with Variable Threshold Voltage (VT) Scheme\" , Proc. CICC'96 , pp. 53 -- 56 , May 1996 . T. Kuroda and al, \"A High-speed Low-power 0.3 μm CMOS Gate Array with Variable Threshold Voltage (VT) Scheme\", Proc. CICC'96, pp. 53--56, May 1996."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea1020277"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1057661.1057713"},{"key":"e_1_3_2_1_15_1","first-page":"779","volume-title":"MWSCAS 2008","year":"2008","unstructured":"Young Bok Kim and al, \"A Technique for Low Power Dynamic Circuit Designin 32nm Double-Gate FinFET Technology \", MWSCAS 2008 , pp 779 -- 782 , Aug. 2008 Young Bok Kim and al, \"A Technique for Low Power Dynamic Circuit Designin 32nm Double-Gate FinFET Technology\", MWSCAS 2008, pp 779--782, Aug. 2008"},{"key":"e_1_3_2_1_16_1","first-page":"2345","article-title":"Low-power spatial computing using dynamic threshold devices","volume":"3","year":"2005","unstructured":"Paul Beckett , \" Low-power spatial computing using dynamic threshold devices \", ISCAS ( ( 3 ) 2005 : 2345 -- 2348 Paul Beckett, \"Low-power spatial computing using dynamic threshold devices\", ISCAS (3) 2005: 2345--2348","journal-title":"ISCAS"},{"volume-title":"Ambipolar Electrical Transport in Semiconducting Single-Wall Carbon Nanotubes\", physical review letters","author":"Martel R.","key":"e_1_3_2_1_17_1","unstructured":"R. Martel , \" Ambipolar Electrical Transport in Semiconducting Single-Wall Carbon Nanotubes\", physical review letters , vol. 87 , no. 25, December 2001 R. Martel et al, \"Ambipolar Electrical Transport in Semiconducting Single-Wall Carbon Nanotubes\", physical review letters, vol. 87, no. 25, December 2001"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.1102896"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1021\/nn900284b"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl051855i"},{"key":"e_1_3_2_1_21_1","first-page":"2562","volume-title":"Actuators and Microsystems Conference (TRANSDUCERS), 2011","author":"Sacchett D.","year":"2011","unstructured":"D. Sacchett Si nanowire field effect transistors for low current and temperature sensing\", Solid-State Sensors , Actuators and Microsystems Conference (TRANSDUCERS), 2011 16th International , pp. 2562 -- 2565 , June 2011 D. Sacchett et al, \"Ambipolar Si nanowire field effect transistors for low current and temperature sensing\", Solid-State Sensors, Actuators and Microsystems Conference (TRANSDUCERS), 2011 16th International, pp. 2562--2565, June 2011"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.269.5230.1560"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.287.5455.1022"},{"key":"e_1_3_2_1_24_1","first-page":"853","volume-title":"Proc. 14th Asia and South Pacific Design Automation Conference (ASP-DAC)","author":"Liu B.","year":"2009","unstructured":"B. Liu , \"Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture\" , Proc. 14th Asia and South Pacific Design Automation Conference (ASP-DAC) , pp. 853 -- 858 , Yokohama, Japan, 19- -22 January 2009 B. Liu, \"Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture\", Proc. 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 853--858, Yokohama, Japan, 19--22 January 2009"},{"key":"e_1_3_2_1_25_1","first-page":"17","volume-title":"Proc. 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","author":"Liu B.","year":"2010","unstructured":"B. Liu , \"Advancements on Crossbar-Based Nanoscale Reconfigurable Computing Platforms\" , Proc. 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) , pp. 17 -- 20 , Seattle (WA), USA, 1- -4 August 2010 B. Liu, \"Advancements on Crossbar-Based Nanoscale Reconfigurable Computing Platforms\", Proc. 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 17--20, Seattle (WA), USA, 1--4 August 2010"},{"key":"e_1_3_2_1_26_1","first-page":"65","volume-title":"Proc. IEEE\/ACM Intl. Symp. Nanoscale Architectures (NANOARCH)","author":"De Marchi M.","year":"2010","unstructured":"M. De Marchi , M. H. Ben Jamaa , G. De Micheli , \"Regular Fabric Design with Ambipolar CNFETs for FPGA and Structured ASIC Applications\" , Proc. IEEE\/ACM Intl. Symp. Nanoscale Architectures (NANOARCH) , pp. 65 -- 70 , Anaheim (CA), USA, 17- -18 June 2010 M. De Marchi, M. H. Ben Jamaa, G. De Micheli, \"Regular Fabric Design with Ambipolar CNFETs for FPGA and Structured ASIC Applications\", Proc. IEEE\/ACM Intl. Symp. Nanoscale Architectures (NANOARCH), pp. 65--70, Anaheim (CA), USA, 17--18 June 2010"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973014"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1149\/1.3567706"},{"key":"e_1_3_2_1_29_1","first-page":"343","volume-title":"3rd IEEE-NANO","volume":"2","author":"Raychowdhury A.","year":"2003","unstructured":"A. Raychowdhury modeling of carbon nanotube FETs in the ballistic limit of performance\" in Proc . 3rd IEEE-NANO , 2003 , vol. 2 , pp. 343 -- 346 . A. Raychowdhury et al, \"Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance\" in Proc. 3rd IEEE-NANO, 2003, vol. 2, pp. 343--346."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1142\/S1793292008000952"},{"volume-title":"IEEE\/ACM international symposium on nanoscale architectures (Nanoarch'10)","year":"2010","key":"e_1_3_2_1_31_1","unstructured":"Kotb. Jabeur et al, \"Reducing transistor count in clocked standard cells with ambipolar double-gate FETs \", IEEE\/ACM international symposium on nanoscale architectures (Nanoarch'10) , june 17--18 2010 , Anaheim, CA, USA. Kotb. Jabeur et al, \"Reducing transistor count in clocked standard cells with ambipolar double-gate FETs\", IEEE\/ACM international symposium on nanoscale architectures (Nanoarch'10), june 17--18 2010, Anaheim, CA, USA."},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.907835"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2011.5941499"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2082548"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851427"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1021\/nl035185x"},{"volume-title":"Ontario, Canada","year":"2004","key":"e_1_3_2_1_37_1","unstructured":"Shahrzad Naraghi, \"Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits\" , Thesis presented to the University of Waterloo , Ontario, Canada 2004 . Shahrzad Naraghi, \"Reduced Swing Domino Techniques for Low Power and High Performance Arithmetic Circuits\", Thesis presented to the University of Waterloo, Ontario, Canada 2004."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.974910"},{"key":"e_1_3_2_1_39_1","unstructured":"http:\/\/ptm.asu.edu\/modelcard\/LP\/16nm_LP.pm  http:\/\/ptm.asu.edu\/modelcard\/LP\/16nm_LP.pm"},{"key":"e_1_3_2_1_40_1","unstructured":"http:\/\/www.allaboutcircuits.com\/vol_4\/chpt_10\/5.html  http:\/\/www.allaboutcircuits.com\/vol_4\/chpt_10\/5.html"},{"key":"e_1_3_2_1_41_1","unstructured":"Chen etal \"Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock\" Patent application number: 20110280353 11\/17\/2011  Chen et al \" Adaptive phase-shifted synchronization clock generation circuit and method for generating phase-shifted synchronization clock \" Patent application number: 20110280353 11\/17\/2011"}],"event":{"name":"NANOARCH '12: IEEE\/ACM International Symposium on Nanoscale Architectures","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation","IEEE CS"],"location":"Amsterdam The Netherlands","acronym":"NANOARCH '12"},"container-title":["Proceedings of the 2012 IEEE\/ACM International Symposium on Nanoscale Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2765491.2765495","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2765491.2765495","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:12:24Z","timestamp":1750227144000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2765491.2765495"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7,4]]},"references-count":41,"alternative-id":["10.1145\/2765491.2765495","10.1145\/2765491"],"URL":"https:\/\/doi.org\/10.1145\/2765491.2765495","relation":{},"subject":[],"published":{"date-parts":[[2012,7,4]]},"assertion":[{"value":"2012-07-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}