{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:15:38Z","timestamp":1750306538671,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2012,7,4]],"date-time":"2012-07-04T00:00:00Z","timestamp":1341360000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2012,7,4]]},"DOI":"10.1145\/2765491.2765503","type":"proceedings-article","created":{"date-parts":[[2015,4,22]],"date-time":"2015-04-22T15:50:56Z","timestamp":1429717856000},"page":"55-60","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":14,"title":["Process\/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors"],"prefix":"10.1145","author":[{"given":"Shashikanth","family":"Bobba","sequence":"first","affiliation":[{"name":"LSI, EPFL, Lausanne, Switzerland"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[{"name":"LSI, EPFL, Lausanne, Switzerland"}]},{"given":"Jian","family":"Zhang","sequence":"additional","affiliation":[{"name":"LSI, EPFL, Lausanne, Switzerland"}]},{"given":"Michele","family":"De Marchi","sequence":"additional","affiliation":[{"name":"LSI, EPFL, Lausanne, Switzerland"}]},{"given":"Davide","family":"Sacchetto","sequence":"additional","affiliation":[{"name":"LSM, EPFL, Lausanne, Switzerland"}]},{"given":"Yusuf","family":"Leblebici","sequence":"additional","affiliation":[{"name":"LSM, EPFL, Lausanne, Switzerland"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[{"name":"LSI, EPFL, Lausanne, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2012,7,4]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228369"},{"key":"e_1_3_2_1_2_1","first-page":"104","article-title":"CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal\/Si for source\/drain contact resistance reduction","author":"Coss B. E.","year":"2009","unstructured":"Coss , B. E. , , \" CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal\/Si for source\/drain contact resistance reduction ,\" Symposium on VLSI Technology 2009 , pp. 104 -- 105 . Coss, B. E., et al., \"CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal\/Si for source\/drain contact resistance reduction,\" Symposium on VLSI Technology 2009, pp. 104--105.","journal-title":"Symposium on VLSI Technology"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2011.5941477"},{"key":"e_1_3_2_1_4_1","first-page":"2320","article-title":"FinFET-a self-aligned double-gate MOSFET scalable to 20 nm","author":"Hisamoto D.","year":"2000","unstructured":"Hisamoto , D. , , \" FinFET-a self-aligned double-gate MOSFET scalable to 20 nm ,\" IEEE Trans. Electron Devices , pp. 2320 -- 2325 , Dec 2000 . Hisamoto, D., et al., \"FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,\" IEEE Trans. Electron Devices, pp. 2320--2325, Dec 2000.","journal-title":"IEEE Trans. Electron Devices"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391556"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851427"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514954"},{"key":"e_1_3_2_1_8_1","first-page":"100","article-title":"Selective phase modulation of NiSi using N-ion implantation for high performance dopant-segregated source\/drain n-channel MOSFETs","author":"Loh W. --Y.","year":"2009","unstructured":"Loh , W. --Y. , , \" Selective phase modulation of NiSi using N-ion implantation for high performance dopant-segregated source\/drain n-channel MOSFETs ,\" Symposium on VLSI Technology 2009 , pp. 100 -- 101 . Loh, W. --Y., et al., \"Selective phase modulation of NiSi using N-ion implantation for high performance dopant-segregated source\/drain n-channel MOSFETs,\" Symposium on VLSI Technology 2009, pp. 100--101.","journal-title":"Symposium on VLSI Technology"},{"key":"e_1_3_2_1_9_1","unstructured":"Open Cell Library 45nm PDK.  Open Cell Library 45nm PDK."},{"key":"e_1_3_2_1_10_1","volume-title":"EDSSC","author":"Ng R.","year":"2007","unstructured":"Ng , R. , Wang , T. , and Chan , M ., \" A new approach to fabricate vertically stacked single-crystalline silicon nanowires,\" IEEE Proc . EDSSC , 2007 . Ng, R., Wang, T., and Chan, M., \"A new approach to fabricate vertically stacked single-crystalline silicon nanowires,\" IEEE Proc. EDSSC, 2007."},{"key":"e_1_3_2_1_11_1","volume-title":"dec","author":"O'Connor I.","year":"2007","unstructured":"O'Connor , I. , Ultra -fine grain reconfigurability using cntfets,\" Proc . ICECS , dec 2007 . O'Connor, I., et al., \"Ultra-fine grain reconfigurability using cntfets,\" Proc. ICECS, dec 2007."},{"volume-title":"CNTFET Modeling and Reconfigurable Logic-Circuit Design,\" IEEE Tran. on Circuits and Systems","author":"O'Connor","key":"e_1_3_2_1_12_1","unstructured":"I. O'Connor , et al. , \" CNTFET Modeling and Reconfigurable Logic-Circuit Design,\" IEEE Tran. on Circuits and Systems , vol. 54 , no. 11, Nov. 2007. I. O'Connor, et al., \"CNTFET Modeling and Reconfigurable Logic-Circuit Design,\" IEEE Tran. on Circuits and Systems, vol. 54, no. 11, Nov. 2007."},{"key":"e_1_3_2_1_13_1","unstructured":"www.opencores.org  www.opencores.org"},{"key":"e_1_3_2_1_14_1","unstructured":"http:\/\/ptm.asu.edu  http:\/\/ptm.asu.edu"},{"key":"e_1_3_2_1_15_1","unstructured":"\"Synopsys design compiler\" 2010.  \"Synopsys design compiler\" 2010."},{"key":"e_1_3_2_1_16_1","unstructured":"\"Cadence Encounter Library Characterizer\" 2010.  \"Cadence Encounter Library Characterizer\" 2010."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863196"},{"key":"e_1_3_2_1_18_1","volume-title":"Proc. ESSDERC","author":"Sacchetto D.","year":"2009","unstructured":"Sacchetto , D. , Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays ,\" Proc. ESSDERC , 2009 . Sacchetto, D., et al., \"Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays,\" Proc. ESSDERC, 2009."},{"key":"e_1_3_2_1_19_1","first-page":"717","article-title":"High performance 5nm radius twin silicon nanowire mosfet (tsnwfet): fabrication on bulk si wafer, characteristics, and reliability","author":"Suk S. D.","year":"2005","unstructured":"Suk , S. D. , , \" High performance 5nm radius twin silicon nanowire mosfet (tsnwfet): fabrication on bulk si wafer, characteristics, and reliability ,\" IEEE Proc., IEDM, dec. 2005 , pp. 717 -- 720 . Suk, S. D., et al., \"High performance 5nm radius twin silicon nanowire mosfet (tsnwfet): fabrication on bulk si wafer, characteristics, and reliability,\" IEEE Proc., IEDM, dec. 2005, pp. 717--720.","journal-title":"IEEE Proc., IEDM, dec."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278568"},{"key":"e_1_3_2_1_21_1","article-title":"Maximization of layout printability\/manufacturability by extreme layout regularity","author":"Tejas J.","year":"2007","unstructured":"Tejas , J. , , \" Maximization of layout printability\/manufacturability by extreme layout regularity ,\" J. Micro\/Nanolith. MEMS , 2007 . Tejas, J., et al., \"Maximization of layout printability\/manufacturability by extreme layout regularity,\" J. Micro\/Nanolith. MEMS, 2007.","journal-title":"J. Micro\/Nanolith. MEMS"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724456"}],"event":{"name":"NANOARCH '12: IEEE\/ACM International Symposium on Nanoscale Architectures","sponsor":["ACM Association for Computing Machinery","SIGDA ACM Special Interest Group on Design Automation","IEEE CS"],"location":"Amsterdam The Netherlands","acronym":"NANOARCH '12"},"container-title":["Proceedings of the 2012 IEEE\/ACM International Symposium on Nanoscale Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2765491.2765503","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2765491.2765503","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:12:24Z","timestamp":1750227144000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2765491.2765503"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,7,4]]},"references-count":22,"alternative-id":["10.1145\/2765491.2765503","10.1145\/2765491"],"URL":"https:\/\/doi.org\/10.1145\/2765491.2765503","relation":{},"subject":[],"published":{"date-parts":[[2012,7,4]]},"assertion":[{"value":"2012-07-04","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}