{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:17:54Z","timestamp":1763468274168,"version":"3.41.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2015,9,9]],"date-time":"2015-09-09T00:00:00Z","timestamp":1441756800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,12,8]]},"abstract":"<jats:p>\n            In recent years, on-chip trace generation has been recognized as a solution to the debugging of increasingly complex software. An\n            <jats:italic>execution trace<\/jats:italic>\n            can be seen as the most fundamentally useful type of trace, allowing the execution path of software to be determined post hoc. However, the bandwidth required to output such a trace can be excessive. Our architecture-aware trace compression (AATC) scheme adds an on-chip branch predictor and branch target buffer to reduce the volume of execution trace data in real time through on-chip compression. Novel redundancy reduction strategies are employed, most notably in exploiting the widespread use of\n            <jats:italic>linked branches<\/jats:italic>\n            and the compiler-driven movement of return addresses between link register, stack, and program counter. In doing so, the volume of\n            <jats:italic>branch target addresses<\/jats:italic>\n            is reduced by 52%, whereas other algorithmic improvements further decrease trace volume. An analysis of spatial and temporal redundancy in the trace stream allows a comparison of encoding strategies to be made for systematically increasing compression performance. A combination of differential, Fibonacci, VarLen, and Move-to-Front encodings are chosen to produce two compressor variants: a performance-focused xAATC that encodes 56.5 instructions\/bit using 24,133 gates and an area-efficient fAATC that encodes 48.1 instructions\/bit using only 9,854 gates.\n          <\/jats:p>","DOI":"10.1145\/2766449","type":"journal-article","created":{"date-parts":[[2015,9,15]],"date-time":"2015-09-15T12:09:15Z","timestamp":1442318955000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Architecture-Aware Real-Time Compression of Execution Traces"],"prefix":"10.1145","volume":"14","author":[{"given":"Bojan","family":"Mihajlovi\u0107","sequence":"first","affiliation":[{"name":"McGill University, Quebec, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"\u017deljko","family":"\u017dili\u0107","sequence":"additional","affiliation":[{"name":"McGill University, Quebec, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Warren J.","family":"Gross","sequence":"additional","affiliation":[{"name":"McGill University, Quebec, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,9,9]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ARM. 2011a. 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Retrieved April 14, 2015, from http:\/\/www.gnu.org\/software\/gdb."},{"key":"e_1_2_1_8_1","volume-title":"Proceedings of the Workshop on Exploiting Concurrency Efficiently and Correctly.","author":"Godefroid Patrice","year":"2008","unstructured":"Patrice Godefroid and Nachiappan Nagappan. 2008. Concurrency at Microsoft: An exploratory survey. In Proceedings of the Workshop on Exploiting Concurrency Efficiently and Correctly."},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/1128020.1128563"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1147\/sj.411.0004"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20050194"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.22"},{"key":"e_1_2_1_13_1","unstructured":"IEEE-ISTO 5001. 2012. The Nexus 5001 Forum Standard for a Global Embedded Processor Debug Interface. Available at http:\/\/nexus5001.org."},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICICIC.2006.207"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956562"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.887613"},{"volume-title":"Multicore Technology: Architecture, Reconfiguration, and Modeling","author":"Mihajlovic Bojan","key":"e_1_2_1_17_1","unstructured":"Bojan Mihajlovic, Warren J. Gross, and Zeljko Zilic. 2013. Software debugging infrastructure for multi-core systems-on-chip. In Multicore Technology: Architecture, Reconfiguration, and Modeling, M. Y. Qadri and S. Sangwine (Eds.). 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