{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:13:05Z","timestamp":1750306385281,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":13,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,6,13]],"date-time":"2015-06-13T00:00:00Z","timestamp":1434153600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,6,13]]},"DOI":"10.1145\/2768177.2768178","type":"proceedings-article","created":{"date-parts":[[2015,7,6]],"date-time":"2015-07-06T14:04:29Z","timestamp":1436191469000},"page":"9-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias"],"prefix":"10.1145","author":[{"given":"Mostafa","family":"Said","sequence":"first","affiliation":[{"name":"Department of Electronics and Communications, Egypt-Japan University of Science and Technology (E-JUST), Alexandria, Egypt"}]},{"given":"Farhad","family":"Mehdipour","sequence":"additional","affiliation":[{"name":"E-JUST Center, Graduate School of Information Science and Electrical Engineering, Kyushu University, Fukuoka, Japan"}]},{"given":"Kazuaki","family":"Murakami","sequence":"additional","affiliation":[{"name":"Department of Advanced Informatics, Kyushu University, Fukuoka, Japan"}]},{"given":"Mohamed","family":"El-Sayed","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communications, Egypt-Japan University of Science and Technology (E-JUST), Alexandria, Egypt"}]}],"member":"320","published-online":{"date-parts":[[2015,6,13]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2013.104"},{"key":"e_1_3_2_1_2_1","first-page":"598","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Loi I.","year":"2008"},{"key":"e_1_3_2_1_3_1","unstructured":"N. Weste D. Harris CMOS VLSI Design A Circuits and Systems Perspective 4th ed. Addison-Wesley 2011.   N. Weste D. Harris CMOS VLSI Design A Circuits and Systems Perspective 4th ed. Addison-Wesley 2011."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/1965079"},{"key":"e_1_3_2_1_5_1","unstructured":"J. Rabaey A. Chandrakasan B. Nikolic Digital Integrated Circuits A Design Perspective 2nd ed. Prentice Hall New Jersey 2003.  J. Rabaey A. Chandrakasan B. Nikolic Digital Integrated Circuits A Design Perspective 2nd ed. Prentice Hall New Jersey 2003."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"crossref","unstructured":"R. Jagtap A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs Master thesis TU Delft 2011.  R. Jagtap A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs Master thesis TU Delft 2011.","DOI":"10.1109\/DSD.2012.9"},{"key":"e_1_3_2_1_7_1","unstructured":"http:\/\/www.itrs.net\/reports.html http:\/\/www.itrs.net\/reports.html"},{"key":"e_1_3_2_1_8_1","unstructured":"J. Uyemura CMOS Logic Circuit Design Kluwer Academic 1999.   J. Uyemura CMOS Logic Circuit Design Kluwer Academic 1999."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.camwa.2012.03.074"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/JEC-ECC.2012.6186980"},{"key":"e_1_3_2_1_11_1","unstructured":"K. Chandrasekar Performance Validation of Networks on Chip Master thesis TU Delft 2009.  K. Chandrasekar Performance Validation of Networks on Chip Master thesis TU Delft 2009."},{"key":"e_1_3_2_1_12_1","first-page":"143","volume-title":"13th International and 10th Symposium on Parallel and Distributed Processing","author":"Avresky D.R.","year":"1999"},{"key":"e_1_3_2_1_13_1","first-page":"294","volume-title":"Proc. MICRO","author":"Wang H.","year":"2002"}],"event":{"name":"MES '15: The third International Workshop on Many-core Embedded Systems","sponsor":["Univ. Turku University of Turku","KTH (The Royal Institute of Technology), Sweden"],"location":"Portland OR USA","acronym":"MES '15"},"container-title":["Proceedings of the 3rd International Workshop on Many-core Embedded Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2768177.2768178","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2768177.2768178","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:07:07Z","timestamp":1750223227000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2768177.2768178"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,13]]},"references-count":13,"alternative-id":["10.1145\/2768177.2768178","10.1145\/2768177"],"URL":"https:\/\/doi.org\/10.1145\/2768177.2768178","relation":{},"subject":[],"published":{"date-parts":[[2015,6,13]]},"assertion":[{"value":"2015-06-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}