{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:14:13Z","timestamp":1750306453365,"version":"3.41.0"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2015,9,24]],"date-time":"2015-09-24T00:00:00Z","timestamp":1443052800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2015,12,8]]},"abstract":"<jats:p>Scaling CMOS technology into nanometer feature-size nodes has made it practically impossible to precisely control the manufacturing process. This results in variation in the speed and power consumption of a circuit. As a solution to process-induced variations, circuits are conventionally implemented with conservative design margins to guarantee the target frequency of each hardware component in manufactured multiprocessor chips. This approach, referred to as worst-case design, results in a considerable circuit upsizing, in turn reducing the number of dies on a wafer.<\/jats:p>\n          <jats:p>\n            This work deals with the design of real-time systems for streaming applications (e.g., video decoders) constrained by a throughput requirement (e.g., frames per second) with reduced design margins, referred to as\n            <jats:italic>better-than-worst-case design<\/jats:italic>\n            . To this end, the first contribution of this work is\n            <jats:italic>a complete modeling framework that captures a streaming application mapped to an NoC-based multiprocessor system with voltage-frequency islands under process-induced die-to-die and within-die frequency variations<\/jats:italic>\n            . The framework is used to analyze the impact of variations in the frequency of hardware components on\n            <jats:italic>application throughput at the system level<\/jats:italic>\n            . The second contribution of this work is\n            <jats:italic>a methodology to use the proposed framework and estimate the impact of reducing circuit design margins on the number of good dies that satisfy the throughput requirement of a real-time streaming application<\/jats:italic>\n            . We show on both synthetic and real applications that the proposed better-than-worst-case design approach can increase the number of good dies by up to 9.6% and 18.8% for designs with and without fixed SRAM and IO blocks, respectively.\n          <\/jats:p>","DOI":"10.1145\/2785968","type":"journal-article","created":{"date-parts":[[2015,9,29]],"date-time":"2015-09-29T19:22:29Z","timestamp":1443554549000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation"],"prefix":"10.1145","volume":"14","author":[{"given":"Davit","family":"Mirzoyan","sequence":"first","affiliation":[{"name":"Delft University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benny","family":"Akesson","sequence":"additional","affiliation":[{"name":"Czech Technical University in Prague"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sander","family":"Stuijk","sequence":"additional","affiliation":[{"name":"Eindhoven University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kees","family":"Goossens","sequence":"additional","affiliation":[{"name":"Eindhoven University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,9,24]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/2492708.2492944"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008052406396"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156225"},{"key":"e_1_2_1_5_1","article-title":"Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hopping for the 80-Core TeraFLOPS processor","volume":"46","author":"Dighe S.","year":"2011","unstructured":"S. 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