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Surv."],"published-print":{"date-parts":[[2015,9,29]]},"abstract":"<jats:p>Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues.<\/jats:p>","DOI":"10.1145\/2785988","type":"journal-article","created":{"date-parts":[[2015,9,29]],"date-time":"2015-09-29T19:22:29Z","timestamp":1443554549000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["Lifetime Reliability Enhancement of Microprocessors"],"prefix":"10.1145","volume":"48","author":[{"given":"Hyejeong","family":"Hong","sequence":"first","affiliation":[{"name":"Yonsei University, Seoul, Korea"}]},{"given":"Jaeil","family":"Lim","sequence":"additional","affiliation":[{"name":"Yonsei University, Seoul, Korea"}]},{"given":"Hyunyul","family":"Lim","sequence":"additional","affiliation":[{"name":"Yonsei University, Seoul, Korea"}]},{"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[{"name":"Yonsei University, Seoul, Korea"}]}],"member":"320","published-online":{"date-parts":[[2015,9,29]]},"reference":[{"volume-title":"Proceedings of the IEEE International Reliability Physics Symposium. 17--22","author":"Abadeer W.","key":"e_1_2_1_1_1","unstructured":"W. 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