{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:14:13Z","timestamp":1750306453647,"version":"3.41.0"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2015,7,8]],"date-time":"2015-07-08T00:00:00Z","timestamp":1436313600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Parallel Comput."],"published-print":{"date-parts":[[2015,7,8]]},"abstract":"<jats:p>As other multithreaded programs, transactional memory (TM) programs are prone to race conditions. Previous work focuses on extending existing definitions of data race for lock-based applications to TM applications, which requires all transactions to be totally ordered \u201cas if\u201d serialized by a global lock. This approach poses implementation constraints on the STM that severely limits TM applications\u2019 performance.<\/jats:p>\n          <jats:p>\n            This article shows that forcing total ordering among all running transactions, while sufficient, is not necessary. We introduce an alternative data race definition,\n            <jats:italic>relaxed transactional data race<\/jats:italic>\n            , that requires ordering of\n            <jats:italic>only<\/jats:italic>\n            conflicting transactions. The advantages of our relaxed definition are twofold: First, unlike the previous definition, this definition can be applied to a wide range of TMs, including those that do not enforce transaction total ordering. Second, within a single execution, it exposes a higher number of data races, which considerably reduces debugging time. Based on this definition, we propose a novel and precise race detection tool for C\/C++ TM applications (TRADE), which detects data races by tracking happens-before edges among conflicting transactions.\n          <\/jats:p>\n          <jats:p>Our experiments reveal that TRADE precisely detects data races for STAMP applications running on modern STMs with overhead comparable to state-of-the-art race detectors for lock-based applications. Our experiments also show that in a single run, TRADE identifies several races not discovered by 10 separate runs of a race detection tool based on the previous data race definition.<\/jats:p>","DOI":"10.1145\/2786021","type":"journal-article","created":{"date-parts":[[2015,7,10]],"date-time":"2015-07-10T14:10:15Z","timestamp":1436537415000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["TRADE"],"prefix":"10.1145","volume":"2","author":[{"given":"Gokcen","family":"Kestor","sequence":"first","affiliation":[{"name":"Pacific Northwest National Laboratory"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Osman S.","family":"Unsal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Adrian","family":"Cristal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Serdar","family":"Tasiran","sequence":"additional","affiliation":[{"name":"Koc University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,7,8]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.ic.2009.09.004"},{"key":"e_1_2_1_2_1","unstructured":"A. Adl-Tabatabai T. Shpeisman and J. Gottschlich. Feb. 2012. Draft Specification for Transactional Features in C++. Version 1.1.  A. Adl-Tabatabai T. Shpeisman and J. Gottschlich. Feb. 2012. Draft Specification for Transactional Features in C++. Version 1.1."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/285930.285996"},{"key":"e_1_2_1_4_1","volume-title":"Proc. of the 1st USENIX Conference on Hot Topics in Parallelism. 15--15","author":"Boehm H.-J.","year":"2009","unstructured":"H.-J. Boehm . 2009 . Transactional memory should be an implementation technique, not a programming interface . In Proc. of the 1st USENIX Conference on Hot Topics in Parallelism. 15--15 . H.-J. Boehm. 2009. Transactional memory should be an implementation technique, not a programming interface. In Proc. of the 1st USENIX Conference on Hot Topics in Parallelism. 15--15."},{"volume-title":"Proc. of the 5th ACM European Conference on Computer Systems.","author":"Christie D.","key":"e_1_2_1_5_1","unstructured":"D. Christie , J. Chung , S. Diestelhorst , M. Hohmuth , M. Pohlack , C. Fetzer , M. Nowack , T. Riegel , P. Felber , P. Marlier , and E. Riviere . 2010. Dresden TM compiler (DTMC) . In Proc. of the 5th ACM European Conference on Computer Systems. D. Christie, J. Chung, S. Diestelhorst, M. Hohmuth, M. Pohlack, C. Fetzer, M. Nowack, T. Riegel, P. Felber, P. Marlier, and E. Riviere. 2010. Dresden TM compiler (DTMC). In Proc. of the 5th ACM European Conference on Computer Systems."},{"key":"e_1_2_1_6_1","unstructured":"TM compiler support in gcc 4.7. 2010. Project Web Site. Retrieved from http:\/\/gcc.gnu.org\/gcc-4.7\/changes.html.  TM compiler support in gcc 4.7. 2010. Project Web Site. Retrieved from http:\/\/gcc.gnu.org\/gcc-4.7\/changes.html."},{"volume-title":"Proc. of the 4th Workshop on Transactional Computing.","author":"Dalessandro L.","key":"e_1_2_1_7_1","unstructured":"L. Dalessandro and M. L. Scott . 2009. Strong isolation is a weak idea . In Proc. of the 4th Workshop on Transactional Computing. L. Dalessandro and M. L. Scott. 2009. Strong isolation is a weak idea. In Proc. of the 4th Workshop on Transactional Computing."},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1693453.1693464"},{"key":"e_1_2_1_9_1","volume-title":"Ajex: A source-to-source Java STM framework compiler. Technical Report. DI-FCT\/UNL.","author":"Dias R.","year":"2009","unstructured":"R. Dias and B. C. Teixeira . 2009 . Ajex: A source-to-source Java STM framework compiler. Technical Report. DI-FCT\/UNL. R. Dias and B. C. Teixeira. 2009. Ajex: A source-to-source Java STM framework compiler. Technical Report. DI-FCT\/UNL."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508263"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/11864219_14"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/122759.122767"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250762"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1542476.1542490"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1178597.1178609"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2009.5161006"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2011.7477488"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065944.1065952"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.23"},{"key":"e_1_2_1_20_1","unstructured":"Intel Corporation. May 2009. Intel Transactional Memory Compiler and Runtime Application Binary Interface. Document No. 318523-002US revision 1.1.  Intel Corporation. May 2009. Intel Transactional Memory Compiler and Runtime Application Binary Interface. Document No. 318523-002US revision 1.1."},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.54"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592809"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/359545.359563"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1378533.1378588"},{"volume-title":"Proc. of the International Symposium on Workload Characterization.","author":"Minh C. C.","key":"e_1_2_1_27_1","unstructured":"C. C. Minh , J. Chung , C. Kozyrakis , and K. Olukotun . 2008. STAMP: Stanford transactional applications for multi-processing . In Proc. of the International Symposium on Workload Characterization. C. C. Minh, J. Chung, C. Kozyrakis, and K. Olukotun. 2008. STAMP: Stanford transactional applications for multi-processing. In Proc. of the International Symposium on Workload Characterization."},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1133981.1134018"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1248377.1248415"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/265924.265927"},{"volume-title":"GCC Research Opportunities Workshop (GROW\u201909)","author":"Schindewolf M.","key":"e_1_2_1_31_1","unstructured":"M. Schindewolf , A. Cohen , W. Karl , A. Marongiu , and L. Benini . 2009. Towards transactional memory support for GCC . In GCC Research Opportunities Workshop (GROW\u201909) . M. Schindewolf, A. Cohen, W. Karl, A. Marongiu, and L. Benini. 2009. Towards transactional memory support for GCC. In GCC Research Opportunities Workshop (GROW\u201909)."},{"key":"e_1_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/73141.74844"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1583991.1584012"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/2103656.2103702"},{"key":"e_1_2_1_35_1","unstructured":"Rochester software transactional memory runtime. 2010. www.cs.rochester.edu\/research\/synchronization\/rstm\/.  Rochester software transactional memory runtime. 2010. www.cs.rochester.edu\/research\/synchronization\/rstm\/."},{"key":"e_1_2_1_36_1","volume-title":"Proc. of InForum","author":"Teixeira B. C.","year":"2010","unstructured":"B. C. Teixeira , J. Lourenco , and D. Sousa . 2010. A static approach for detecting concurrency anomalies in transactional memory . In Proc. of InForum 2010 . B. C. Teixeira, J. Lourenco, and D. Sousa. 2010. A static approach for detecting concurrency anomalies in transactional memory. In Proc. of InForum 2010."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/504282.504288"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/1693453.1693463"}],"container-title":["ACM Transactions on Parallel Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786021","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2786021","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:43:15Z","timestamp":1750225395000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786021"}},"subtitle":["Precise Dynamic Race Detection for Scalable Transactional Memory Systems"],"short-title":[],"issued":{"date-parts":[[2015,7,8]]},"references-count":37,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2015,7,8]]}},"alternative-id":["10.1145\/2786021"],"URL":"https:\/\/doi.org\/10.1145\/2786021","relation":{},"ISSN":["2329-4949","2329-4957"],"issn-type":[{"type":"print","value":"2329-4949"},{"type":"electronic","value":"2329-4957"}],"subject":[],"published":{"date-parts":[[2015,7,8]]},"assertion":[{"value":"2013-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-07-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}