{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T14:15:57Z","timestamp":1761401757943,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,9,28]],"date-time":"2015-09-28T00:00:00Z","timestamp":1443398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,9,28]]},"DOI":"10.1145\/2786572.2786595","type":"proceedings-article","created":{"date-parts":[[2015,8,26]],"date-time":"2015-08-26T16:48:13Z","timestamp":1440607693000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":28,"title":["Improving DVFS in NoCs with Coherence Prediction"],"prefix":"10.1145","author":[{"given":"Robert","family":"Hesse","sequence":"first","affiliation":[{"name":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada"}]},{"given":"Natalie Enright","family":"Jerger","sequence":"additional","affiliation":[{"name":"Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada"}]}],"member":"320","published-online":{"date-parts":[[2015,9,28]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665691"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.32"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.12"},{"key":"e_1_3_2_1_7_1","first-page":"147","volume-title":"Internationa Conference on VLSI and System-on-Chip (VLSI-SoC)","author":"David R.","year":"2012","unstructured":"R. David , P. Bogdan , and R. Marculescu . Dynamic power management for multicores: Case study using the Intel SCC . In Internationa Conference on VLSI and System-on-Chip (VLSI-SoC) , pages 147 -- 152 , Oct 2012 . R. David, P. Bogdan, and R. Marculescu. Dynamic power management for multicores: Case study using the Intel SCC. In Internationa Conference on VLSI and System-on-Chip (VLSI-SoC), pages 147--152, Oct 2012."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2016604.2016611"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.40"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008373903657"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079450"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"e_1_3_2_1_13_1","first-page":"123","volume-title":"International Symposium on High Performance Computer Architecture","author":"Kim W.","year":"2008","unstructured":"W. Kim , M. Gupta , G.-Y. Wei , and D. Brooks . System level analysis of fast, per-core DVFS using on-chip switching regulators . In International Symposium on High Performance Computer Architecture , pages 123 -- 134 , Feb 2008 . W. Kim, M. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. In International Symposium on High Performance Computer Architecture, pages 123--134, Feb 2008."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2006.21"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859642"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669151"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/785166.785316"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2011229"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2011.03.016"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2002.10"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2257900"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835941"}],"event":{"name":"NOCS '15: International Symposium on Networks-on-Chip","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Vancouver BC Canada","acronym":"NOCS '15"},"container-title":["Proceedings of the 9th International Symposium on Networks-on-Chip"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786572.2786595","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2786572.2786595","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:43:08Z","timestamp":1750225388000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786572.2786595"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9,28]]},"references-count":22,"alternative-id":["10.1145\/2786572.2786595","10.1145\/2786572"],"URL":"https:\/\/doi.org\/10.1145\/2786572.2786595","relation":{},"subject":[],"published":{"date-parts":[[2015,9,28]]},"assertion":[{"value":"2015-09-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}