{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:14:10Z","timestamp":1750306450698,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,9,28]],"date-time":"2015-09-28T00:00:00Z","timestamp":1443398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,9,28]]},"DOI":"10.1145\/2786572.2786598","type":"proceedings-article","created":{"date-parts":[[2015,8,26]],"date-time":"2015-08-26T16:48:13Z","timestamp":1440607693000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC"],"prefix":"10.1145","author":[{"given":"Pooria M.","family":"Yaghini","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of California, Irvine"}]},{"given":"Ashkan","family":"Eghbal","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of California, Irvine"}]},{"given":"Siavash S.","family":"Yazdi","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of California, Irvine"}]},{"given":"Nader","family":"Bagherzadeh","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Science, University of California, Irvine"}]}],"member":"320","published-online":{"date-parts":[[2015,9,28]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"62","volume-title":"ASICON '09. IEEE 8th International Conference on, Oct.","author":"Lu Z.","unstructured":"Z. Lu and A. Jantsch , \" Trends of terascale computing chips in the next ten years,\" in ASIC, 2009 . ASICON '09. IEEE 8th International Conference on, Oct. , pp. 62 -- 66 . Z. Lu and A. Jantsch, \"Trends of terascale computing chips in the next ten years,\" in ASIC, 2009. ASICON '09. IEEE 8th International Conference on, Oct., pp. 62--66."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2010.09.031"},{"key":"e_1_3_2_1_3_1","first-page":"13","volume-title":"Springer US","author":"Burns J.","year":"2011","unstructured":"J. Burns , \"Tsv-based 3d integration,\" in Three Dimensional System Integration , A. Papanikolaou , D. Soudris , and R. Radojcic , Eds . Springer US , 2011 , pp. 13 -- 32 . J. Burns, \"Tsv-based 3d integration,\" in Three Dimensional System Integration, A. Papanikolaou, D. Soudris, and R. Radojcic, Eds. Springer US, 2011, pp. 13--32."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026200"},{"key":"e_1_3_2_1_5_1","first-page":"1","volume-title":"IEEE International Conference on","author":"Weerasekera R.","year":"2009","unstructured":"R. Weerasekera , M. Grange , D. Pamunuwa , H. Tenhunen , and L.-R. Zheng , \"Compact modelling of through-silicon vias (tsvs) in three-dimensional (3-d) integrated circuits,\" in 3D System Integration, 2009. 3DIC 2009 . IEEE International Conference on , 2009 , pp. 1 -- 8 . R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L.-R. Zheng, \"Compact modelling of through-silicon vias (tsvs) in three-dimensional (3-d) integrated circuits,\" in 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on, 2009, pp. 1--8."},{"key":"e_1_3_2_1_6_1","first-page":"87","volume-title":"2012 Symposium on","author":"Jeddeloh J.","year":"2012","unstructured":"J. Jeddeloh and B. Keeth , \" Hybrid memory cube new dram architecture increases density and performance,\" in VLSI Technology (VLSIT) , 2012 Symposium on , June 2012 , pp. 87 -- 88 . J. Jeddeloh and B. Keeth, \"Hybrid memory cube new dram architecture increases density and performance,\" in VLSI Technology (VLSIT), 2012 Symposium on, June 2012, pp. 87--88."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2522968.2522976"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/2492708.2492791"},{"key":"e_1_3_2_1_9_1","first-page":"424","volume-title":"2014 32nd IEEE International Conference on","author":"Iordanou C.","year":"2014","unstructured":"C. Iordanou , V. Soteriou , and K. Aisopos , \" Hermes: Architecting a top-performing fault-tolerant routing algorithm for networks-on-chips,\" in Computer Design (ICCD) , 2014 32nd IEEE International Conference on , Oct 2014 , pp. 424 -- 431 . C. Iordanou, V. Soteriou, and K. Aisopos, \"Hermes: Architecting a top-performing fault-tolerant routing algorithm for networks-on-chips,\" in Computer Design (ICCD), 2014 32nd IEEE International Conference on, Oct 2014, pp. 424--431."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2010.512016"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.27"},{"key":"e_1_3_2_1_12_1","first-page":"1","article-title":"Abd El Ghany, and K. Hofmann, \"Performability of error control schemes for noc interconnects","volume":"2012","author":"Zamzam D.","year":"2012","unstructured":"D. Zamzam , M . Abd El Ghany, and K. Hofmann, \"Performability of error control schemes for noc interconnects ,\" in NORCHIP , 2012 , No v 2012 , pp. 1 -- 5 . D. Zamzam, M. Abd El Ghany, and K. Hofmann, \"Performability of error control schemes for noc interconnects,\" in NORCHIP, 2012, Nov 2012, pp. 1--5.","journal-title":"NORCHIP"},{"key":"e_1_3_2_1_13_1","first-page":"1","volume-title":"2015 IEEE 33rd","author":"Eghbal A.","year":"2015","unstructured":"A. Eghbal , P. M. Yaghini , and N. Bagherzadeh , \" Capacitive coupling mitigation for tsv-based 3d ics,\" in VLSI Test Symposium (VTS) , 2015 IEEE 33rd , April 2015 , pp. 1 -- 6 . A. Eghbal, P. M. Yaghini, and N. Bagherzadeh, \"Capacitive coupling mitigation for tsv-based 3d ics,\" in VLSI Test Symposium (VTS), 2015 IEEE 33rd, April 2015, pp. 1--6."},{"key":"e_1_3_2_1_14_1","first-page":"92","volume-title":"2014 IEEE International Symposium on","author":"Eghbal A.","year":"2014","unstructured":"A. Eghbal , P. Yaghini , S. Yazdi , and N. Bagherzadeh , \" Tsv-to-tsv inductive coupling-aware coding scheme for 3d network-on-chip,\" in Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , 2014 IEEE International Symposium on , Oct 2014 , pp. 92 -- 97 . A. Eghbal, P. Yaghini, S. Yazdi, and N. Bagherzadeh, \"Tsv-to-tsv inductive coupling-aware coding scheme for 3d network-on-chip,\" in Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 IEEE International Symposium on, Oct 2014, pp. 92--97."},{"key":"e_1_3_2_1_15_1","first-page":"1","volume-title":"2014 27th International Conference on","author":"Mohammadian F.","year":"2014","unstructured":"F. Mohammadian , \"Falp : A fault adaptive and low power method for network on chip router,\" in Architecture of Computing Systems (ARCS) , 2014 27th International Conference on , Feb 2014 , pp. 1 -- 7 . F. Mohammadian, \"Falp: A fault adaptive and low power method for network on chip router,\" in Architecture of Computing Systems (ARCS), 2014 27th International Conference on, Feb 2014, pp. 1--7."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDP.2012.82"},{"issue":"99","key":"e_1_3_2_1_17_1","first-page":"1","article-title":"Analytical fault tolerance assessment and metrics for tsv-based 3d network-on-chip","author":"Eghbal A.","year":"2015","unstructured":"A. Eghbal , P. M. Yaghini , N. Bagherzadeh , and M. Khayambashi , \" Analytical fault tolerance assessment and metrics for tsv-based 3d network-on-chip ,\" Computers, IEEE Transactions on , vol. PP, no. 99 , pp. 1 -- 1 , 2015 . A. Eghbal, P. M.Yaghini, N. Bagherzadeh, and M. Khayambashi, \"Analytical fault tolerance assessment and metrics for tsv-based 3d network-on-chip,\" Computers, IEEE Transactions on, vol. PP, no. 99, pp. 1--1, 2015.","journal-title":"Computers, IEEE Transactions on"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024931"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/505306.505331"},{"key":"e_1_3_2_1_20_1","first-page":"762","volume-title":"2014 19th Asia and South Pacific","author":"Zou Q.","year":"2014","unstructured":"Q. Zou , D. Niu , Y. Cao , and Y. Xie , \" 3dlat: Tsv-based 3d ics crosstalk minimization utilizing less adjacent transition code,\" in Design Automation Conference (ASP-DAC) , 2014 19th Asia and South Pacific , Jan 2014 , pp. 762 -- 767 . Q. Zou, D. Niu, Y. Cao, and Y. Xie, \"3dlat: Tsv-based 3d ics crosstalk minimization utilizing less adjacent transition code,\" in Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific, Jan 2014, pp. 762--767."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1002\/mop.26021"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024900"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2101910"},{"key":"e_1_3_2_1_24_1","first-page":"281","volume-title":"2013 IEEE\/ACM International Conference on","author":"Peng Y.","year":"2013","unstructured":"Y. Peng , T. Song , D. Petranovic , and S. K. Lim , \" On accurate full-chip extraction and optimization of tsv-to-tsv coupling elements in 3d ics,\" in Computer-Aided Design (ICCAD) , 2013 IEEE\/ACM International Conference on , Nov 2013 , pp. 281 -- 288 . Y. Peng, T. Song, D. Petranovic, and S. K. Lim, \"On accurate full-chip extraction and optimization of tsv-to-tsv coupling elements in 3d ics,\" in Computer-Aided Design (ICCAD), 2013 IEEE\/ACM International Conference on, Nov 2013, pp. 281--288."},{"key":"e_1_3_2_1_25_1","unstructured":"S. Itr \"ITRS 2012 Executive Summary \" ITRS.  S. Itr \"ITRS 2012 Executive Summary \" ITRS."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/2631408"},{"key":"e_1_3_2_1_27_1","unstructured":"PTM \"Predictive technology model.\" {Online}. Available: http:\/\/ptm.asu.edu  PTM \"Predictive technology model.\" {Online}. Available: http:\/\/ptm.asu.edu"},{"key":"e_1_3_2_1_28_1","unstructured":"THENoC \"3d noc simulator.\" {Online}. Available: gram.eng.uci.edu\/comp.arch\/lab\/tools.html  THENoC \"3d noc simulator.\" {Online}. Available: gram.eng.uci.edu\/comp.arch\/lab\/tools.html"}],"event":{"name":"NOCS '15: International Symposium on Networks-on-Chip","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA","SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Vancouver BC Canada","acronym":"NOCS '15"},"container-title":["Proceedings of the 9th International Symposium on Networks-on-Chip"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786572.2786598","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2786572.2786598","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:43:08Z","timestamp":1750225388000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2786572.2786598"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9,28]]},"references-count":28,"alternative-id":["10.1145\/2786572.2786598","10.1145\/2786572"],"URL":"https:\/\/doi.org\/10.1145\/2786572.2786598","relation":{},"subject":[],"published":{"date-parts":[[2015,9,28]]},"assertion":[{"value":"2015-09-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}