{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:16:29Z","timestamp":1750306589195,"version":"3.41.0"},"publisher-location":"New York, New York, USA","reference-count":32,"publisher":"ACM Press","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100000780","name":"European Commission","doi-asserted-by":"publisher","award":["FP7-318633"],"award-info":[{"award-number":["FP7-318633"]}],"id":[{"id":"10.13039\/501100000780","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015]]},"DOI":"10.1145\/2791321.2791331","type":"proceedings-article","created":{"date-parts":[[2015,12,1]],"date-time":"2015-12-01T14:48:00Z","timestamp":1448981280000},"page":"1-10","source":"Crossref","is-referenced-by-count":10,"title":["CHO"],"prefix":"10.1145","author":[{"given":"Geoffrey","family":"Ndu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Javier","family":"Navaridas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mikel","family":"Luj\u00e1n","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","reference":[{"key":"key-10.1145\/2791321.2791331-1","unstructured":"AILab. http:\/\/www-ailab.elcom.nitech.ac.jp."},{"key":"key-10.1145\/2791321.2791331-2","unstructured":"Clang. http:\/\/clang.llvm.org."},{"key":"key-10.1145\/2791321.2791331-3","unstructured":"Altera SDK for OpenCL: Optimization Guide. Dec. 2013."},{"key":"key-10.1145\/2791321.2791331-4","doi-asserted-by":"crossref","unstructured":"V. H. Allan, R. B. Jones, R. M. Lee, and S. J. Allan. Software pipelining.ACM Comput. Surv., 27(3):367--432, Sept. 1995.","DOI":"10.1145\/212094.212131"},{"key":"key-10.1145\/2791321.2791331-5","unstructured":"Altera Corporation.Altera SDK for OpenCL: Programming Guide, ocl002-13.1.1 edition, Dec. 2013."},{"key":"key-10.1145\/2791321.2791331-6","doi-asserted-by":"crossref","unstructured":"O. Arcas-Abella, G. Ndu, N. Sonmez, M. Ghasempour, A. Armejach, J. Navaridas, W. Song, J. Mawer, A. Cristal, and M. Lujan. An empirical evaluation of high-level synthesis languages and tools for database acceleration. InField Programmable Logic and Applications (FPL), 2014 24th International Conference on, pages 1--8, Sept 2014.","DOI":"10.1109\/FPL.2014.6927484"},{"key":"key-10.1145\/2791321.2791331-7","doi-asserted-by":"crossref","unstructured":"S. Che, J. Sheaffer, M. Boyer, L. Szafaryn, L. Wang, and K. Skadron. A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads. InWorkload Characterization (IISWC), 2010 IEEE International Symposium on, pages 1--11, Dec 2010.","DOI":"10.1109\/IISWC.2010.5650274"},{"key":"key-10.1145\/2791321.2791331-8","doi-asserted-by":"crossref","unstructured":"D. Chen and D. Singh. Fractal video compression in OpenCL: An evaluation of CPUs, GPUs, and FPGAs as acceleration platforms. InDesign Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, pages 297--304, Jan 2013.","DOI":"10.1109\/ASPDAC.2013.6509612"},{"key":"key-10.1145\/2791321.2791331-9","doi-asserted-by":"crossref","unstructured":"L. Chunho, M. Potkonjak, and W. Mangione-Smith. Mediabench: a tool for evaluating and synthesizing multimedia and communications systems. InMicroarchitecture, 1997. Proceedings., Thirtieth Annual IEEE\/ACM International Symposium on, pages 330--335, Dec 1997.","DOI":"10.1109\/MICRO.1997.645830"},{"key":"key-10.1145\/2791321.2791331-10","doi-asserted-by":"crossref","unstructured":"P. Coussy, D. Gajski, M. Meredith, and A. Takach. An Introduction to High-Level Synthesis.Design Test of Computers, IEEE, 26(4):8--17, July 2009.","DOI":"10.1109\/MDT.2009.69"},{"key":"key-10.1145\/2791321.2791331-11","doi-asserted-by":"crossref","unstructured":"T. Czajkowski, U. Aydonat, D. Denisenko, J. Freeman, M. Kinsner, D. Neto, J. Wong, P. Yiannacouras, and D. Singh. From opencl to high-performance hardware on FPGAS. InField Programmable Logic and Applications (FPL), 2012 22nd International Conference on, pages 531--534, Aug 2012.","DOI":"10.1109\/FPL.2012.6339272"},{"key":"key-10.1145\/2791321.2791331-12","doi-asserted-by":"crossref","unstructured":"A. Danalis, G. Marin, C. McCurdy, J. S. Meredith, P. C. Roth, K. Spafford, V. Tipparaju, and J. S. Vetter. The Scalable Heterogeneous Computing (SHOC) Benchmark Suite. InProceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU '10, pages 63--74, 2010.","DOI":"10.1145\/1735688.1735702"},{"key":"key-10.1145\/2791321.2791331-13","unstructured":"H. G. Dietz. The Aggregate Magic Algorithms. Technical report, University of Kentucky."},{"key":"key-10.1145\/2791321.2791331-14","unstructured":"N. Dutt. Benchmarks for the 1992 High Level Synthesis Workshop. 1992."},{"key":"key-10.1145\/2791321.2791331-15","doi-asserted-by":"crossref","unstructured":"D. D. Gajski, S. Abdi, A. Gerstlauer, and G. Schirner.Embedded System Design: Modeling, Synthesis and Verification.2009.","DOI":"10.1007\/978-1-4419-0504-8"},{"key":"key-10.1145\/2791321.2791331-16","doi-asserted-by":"crossref","unstructured":"M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown. MiBench: A free, commercially representative embedded benchmark suite. InWorkload Characterization, 2001. WWC-4. 2001 IEEE International Workshop on, pages 3--14, Dec 2001.","DOI":"10.1109\/WWC.2001.990739"},{"key":"key-10.1145\/2791321.2791331-17","doi-asserted-by":"crossref","unstructured":"Y. Hara, H. Tomiyama, S. Honda, and H. Takada. Proposal and quantitative analysis of the chstone benchmark program suite for practical c-based high-level synthesis.Journal of Information Processing, 17:242--254, 2009.","DOI":"10.2197\/ipsjjip.17.242"},{"key":"key-10.1145\/2791321.2791331-18","unstructured":"J. R. Hauser. SoftFloat Release 2b General Documentation. 2007."},{"key":"key-10.1145\/2791321.2791331-19","doi-asserted-by":"crossref","unstructured":"Q. Huang, R. Lian, A. Canis, J. Choi, R. Xi, S. Brown, and J. Anderson. The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. InField-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on, pages 89--96, April 2013.","DOI":"10.1109\/FCCM.2013.50"},{"key":"key-10.1145\/2791321.2791331-20","unstructured":"A. C. Hung. PVRG-JPEG CODEC 1.1. Technical report, Stanford University, 1993."},{"key":"key-10.1145\/2791321.2791331-21","doi-asserted-by":"crossref","unstructured":"Khronos Group Inc. The OpenCL Specification Version: 1.0, June 2009.","DOI":"10.1109\/HOTCHIPS.2009.7478341"},{"key":"key-10.1145\/2791321.2791331-22","doi-asserted-by":"crossref","unstructured":"D. Koch and J. Torresen. FPGASort: A high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting. InProceedings of the 19th ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, pages 45--54, 2011.","DOI":"10.1145\/1950413.1950427"},{"key":"key-10.1145\/2791321.2791331-23","doi-asserted-by":"crossref","unstructured":"C. Lattner and V. Adve. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. InProceedings of the 2004 International Symposium on Code Generation and Optimization (CGO'04), Mar 2004.","DOI":"10.1109\/CGO.2004.1281665"},{"key":"key-10.1145\/2791321.2791331-24","doi-asserted-by":"crossref","unstructured":"J. Liu, M. Chang, and C.-K. Cheng. An Iterative Division Algorithm for FPGAs. InProceedings of the 14th ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '06, pages 83--89, 2006.","DOI":"10.1145\/1117201.1117213"},{"key":"key-10.1145\/2791321.2791331-25","unstructured":"Memory & Storage Architecture Lab@Seoul National University. SNU Real-Time Benchmarks. http:\/\/archi.snu.ac.kr\/realtime\/benchmark."},{"key":"key-10.1145\/2791321.2791331-26","doi-asserted-by":"crossref","unstructured":"P. Mistry, Y. Ukidave, D. Schaa, and D. Kaeli. Valar: A Benchmark Suite to Study the Dynamic Behavior of Heterogeneous Systems. InProceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, GPGPU-6, pages 54--65, 2013.","DOI":"10.1145\/2458523.2458529"},{"key":"key-10.1145\/2791321.2791331-27","unstructured":"K. Morris. HLS versus OpenCL Xilinx and Altera Square Off on the Future.Electronic Engineering Journal, March 2013."},{"key":"key-10.1145\/2791321.2791331-28","doi-asserted-by":"crossref","unstructured":"G. Ndu, J. Navaridas, and M. Lujan. CHO: A Benchmark Suite for OpenCL-based FPGA Accelerators. Technical report, University of Manchester, May 2014.","DOI":"10.1145\/2791321.2791331"},{"key":"key-10.1145\/2791321.2791331-29","doi-asserted-by":"crossref","unstructured":"M. Owaida, N. Bellas, K. Daloukas, and C. Antonopoulos. Synthesis of Platform Architectures from OpenCL Programs. InField-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on, pages 186--193, May 2011.","DOI":"10.1109\/FCCM.2011.19"},{"key":"key-10.1145\/2791321.2791331-30","doi-asserted-by":"crossref","unstructured":"P. Panda and N. Dutt. 1995 high level synthesis design repository. InSystem Synthesis, 1995., Proceedings of the Eighth International Symposium on, pages 170--174, Sep 1995.","DOI":"10.1109\/ISSS.1995.520630"},{"key":"key-10.1145\/2791321.2791331-31","doi-asserted-by":"crossref","unstructured":"D. B. Thomas, L. Howes, and W. Luk. A Comparison of CPUs, GPUs, FPGAs, and Massively Parallel Processor Arrays for Random Number Generation. InProceedings of the 17th ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '09, pages 63--72, 2009.","DOI":"10.1145\/1508128.1508139"},{"key":"key-10.1145\/2791321.2791331-32","unstructured":"Xilinx.com. Sdaccel development environment. http:\/\/www.xilinx.com\/products\/design-tools\/sdx\/sdaccel.html, 2015."}],"event":{"number":"3","sponsor":["AMD","Altera Corp., Altera Corporation","Auviz, Auviz Systems","Codeplay, Codeplay Software Ltd.","Imagination, Imagination Technologies Limited","hgpu.org, high performance computing on graphics processing units","QI, Qualcomm Inc.","The University of Bristol","Khronos, Khronos Group"],"acronym":"IWOCL '15","name":"the 3rd International Workshop","start":{"date-parts":[[2015,5,12]]},"location":"Palo Alto, California","end":{"date-parts":[[2015,5,13]]}},"container-title":["Proceedings of the 3rd International Workshop on OpenCL - IWOCL '15"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2791321.2791331","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/dl.acm.org\/ft_gateway.cfm?id=2791331&ftid=1648735&dwn=1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T06:16:28Z","timestamp":1750227388000},"score":1,"resource":{"primary":{"URL":"http:\/\/dl.acm.org\/citation.cfm?doid=2791321.2791331"}},"subtitle":["towards a benchmark suite for OpenCL FPGA accelerators"],"proceedings-subject":"OpenCL","short-title":[],"issued":{"date-parts":[[2015]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1145\/2791321.2791331","relation":{},"subject":[],"published":{"date-parts":[[2015]]}}}