{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:49:30Z","timestamp":1750308570502,"version":"3.41.0"},"reference-count":50,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2016,3,8]],"date-time":"2016-03-08T00:00:00Z","timestamp":1457395200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation","award":["CCF-1318603"],"award-info":[{"award-number":["CCF-1318603"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2016,7,26]]},"abstract":"<jats:p>The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology nodes. Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. In this article, we propose a delay\/power modeling framework for analysis of FinFET logic circuits under PVT variations. We present models for FinFET logic gates and three FinFET SRAM cells. We use GenFin, which is a genetic algorithm based statistical circuit-level delay\/power optimizer, to produce the models for functional units (FUs) employed in a processor. We compare the impact of PVT variations at the 22nm and 14nm FinFET technology nodes. We evaluate cache performance for various cache capacities and temperatures as well as that of FUs. Our device simulation results show that the 3\u03c3\/\u03bc spread for 14nm circuits is, on average, 38.5% higher in dynamic power and 21.4% higher in logarithm of leakage power relative to 22nm FinFET circuits. However, the delay spread depends on the circuit.<\/jats:p>","DOI":"10.1145\/2795231","type":"journal-article","created":{"date-parts":[[2016,3,14]],"date-time":"2016-03-14T13:24:02Z","timestamp":1457961842000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Delay\/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations"],"prefix":"10.1145","volume":"12","author":[{"given":"Aoxiang","family":"Tang","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Xun","family":"Gao","sequence":"additional","affiliation":[{"name":"Wuhan University, Hubei, China"}]},{"given":"Lung-Yen","family":"Chen","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}]}],"member":"320","published-online":{"date-parts":[[2016,3,8]]},"reference":[{"volume-title":"Retrieved","year":"2005","author":"Adya Saurabh","key":"e_1_2_1_1_1"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009993"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887809"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1877745.1877746"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2227850"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2227848"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887810"},{"volume-title":"Proceedings of the 2006 IEEE International SOI Conference. 105--106","author":"Carlson A.","key":"e_1_2_1_8_1"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.5555\/996070.1009954"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065716"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850834"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2567670"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2006.306040"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233620"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000726"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.728914"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2017428"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.13"},{"key":"e_1_2_1_19_1","unstructured":"Mark A. Horowitz. 1983. Timing Models for MOS Circuits. Technical Report. Stanford CA.   Mark A. Horowitz. 1983. Timing Models for MOS Circuits. Technical Report. Stanford CA."},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2006043"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/16.918235"},{"volume-title":"Retrieved","year":"2012","author":"ITRS.","key":"e_1_2_1_22_1"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.88"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2202392"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774593"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2260569"},{"volume-title":"Proceedings of the International Symposium on Networks-on-Chip. 117--126","year":"2008","author":"Li B.","key":"e_1_2_1_27_1"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2010.5641060"},{"volume-title":"Proceedings of the International Symposium on VLSI Technology. 16--17","author":"Lin C.-H.","key":"e_1_2_1_30_1"},{"volume-title":"Proceedings of the International Conference on Computer-Aided Design. 639--644","year":"2005","author":"Liu P.","key":"e_1_2_1_31_1"},{"volume-title":"Proceedings of the International Symposium on Quality of Electronic Design. 347--355","author":"Mishra P.","key":"e_1_2_1_32_1"},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.129"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871549"},{"volume-title":"Proceedings of the International Conference on Computer Design. 560--567","year":"2007","author":"Muttreja A.","key":"e_1_2_1_35_1"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2008.59"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2011.6035034"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001140"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882482"},{"key":"e_1_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.893544"},{"key":"e_1_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871529"},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147047"},{"key":"e_1_2_1_43_1","unstructured":"Synopsys. 2012. Sentaurus TCAD Manuals. (2012). Available for download at http:\/\/www.synopsys.com.  Synopsys. 2012. Sentaurus TCAD Manuals. (2012). Available for download at http:\/\/www.synopsys.com."},{"key":"e_1_2_1_44_1","first-page":"1","article-title":"GenFin: Genetic algorithm-based multiobjective statistical FinFET logic circuit optimization using incremental statistical analysis","volume":"99","author":"Tang A.","year":"2015","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems PP"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2352354"},{"key":"e_1_2_1_46_1","unstructured":"Shyamkumar Thoziyoor Naveen Muralimanohar Jung Ho Ahn and Norman P. Jouppi. 2008. Cacti5.1 Technical Report. Technical Report. HP Laboratories Palo Alto CA.  Shyamkumar Thoziyoor Naveen Muralimanohar Jung Ho Ahn and Norman P. Jouppi. 2008. Cacti5.1 Technical Report. Technical Report. HP Laboratories Palo Alto CA."},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862751"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882589"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293886"},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2142183"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2795231","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2795231","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T19:04:27Z","timestamp":1750273467000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2795231"}},"subtitle":["Observing the Trends between the 22nm and 14nm Technology Nodes"],"short-title":[],"issued":{"date-parts":[[2016,3,8]]},"references-count":50,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2016,7,26]]}},"alternative-id":["10.1145\/2795231"],"URL":"https:\/\/doi.org\/10.1145\/2795231","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2016,3,8]]},"assertion":[{"value":"2014-12-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-06-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2016-03-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}