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Syst."],"published-print":{"date-parts":[[2016,1,28]]},"abstract":"<jats:p>Developing circuits for streaming applications written in C (or its variants) can benefit greatly from C-to-RTL (C2RTL) synthesis. Yet, most existing C2RTL tools lack system-level options to trade off various design constraints, such as delay and area. This article introduces a systematic way to accomplish C2RTL synthesis for streaming applications containing thousands of lines of C (or its variants) codes. Synthesizing circuits for such large applications presents serious challenges for existing C2RTL tools. Specifically, the proposed approach determines simultaneously the number of pipeline stages and the number of times that each functional block is duplicated in each pipeline stage. A mixed integer linear programming-based solution is formulated for obtaining the optimal solution. Furthermore, a heuristic algorithm is developed for large-scale problems. To accommodate the differences of the data rates between the adjacent hardware modules, first-in-first-out (FIFO) buffers are indispensable, but their overheads are nonnegligible. A parallelism-aware FIFO sizing method is also introduced to determine the optimal sizes of FIFOs. Experimental results on seven real-world applications demonstrate that the algorithms in the synthesis flow can make effective design trade-offs and find superior solutions in a short time compared with existing approaches. Furthermore, the algorithms achieve optimal results in most cases with subsecond running time.<\/jats:p>","DOI":"10.1145\/2797135","type":"journal-article","created":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T20:37:54Z","timestamp":1454359074000},"page":"1-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications"],"prefix":"10.1145","volume":"21","author":[{"given":"Daming","family":"Zhang","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuangchen","family":"Li","sequence":"additional","affiliation":[{"name":"University of California, Santa Barbara, Santa Barbara, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaobo Sharon","family":"Hu","sequence":"additional","affiliation":[{"name":"University of Notre Dame, Notre Dame"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinyu","family":"He","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yining","family":"Zhang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pei","family":"Zhang","sequence":"additional","affiliation":[{"name":"Y Explorations, Inc., San Jose, CA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,1,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488747"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2514641.2514652"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391663"},{"volume-title":"Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASPDAC'12)","author":"Chen Y.","key":"e_1_2_1_4_1","unstructured":"Y. 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In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC'10). 809--814."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2209291.2209302"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2348839.2348845"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554780"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488748"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2008.10"},{"key":"e_1_2_1_40_1","unstructured":"Xilinx. 2015. Vivado high-level synthesis. http:\/\/www.xilinx.com\/.  Xilinx. 2015. Vivado high-level synthesis. http:\/\/www.xilinx.com\/."},{"key":"e_1_2_1_41_1","unstructured":"YXI. 2013. YXI's eXCite tool. http:\/\/www.yxi.com\/.  YXI. 2013. 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