{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:13:59Z","timestamp":1750306439964,"version":"3.41.0"},"reference-count":41,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2015,12,2]],"date-time":"2015-12-02T00:00:00Z","timestamp":1449014400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"ANR research project FAMOUS"},{"DOI":"10.13039\/501100001665","name":"French National Research Agency","doi-asserted-by":"crossref","award":["ANR-009-SEGI-003"],"award-info":[{"award-number":["ANR-009-SEGI-003"]}],"id":[{"id":"10.13039\/501100001665","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2015,12,2]]},"abstract":"<jats:p>This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of correct by construction reconfiguration controller. This article builds upon previous research by integrating previously separated endeavors to obtain a complete PR system generation chain, which aims at shielding the designer of many of the burdensome technological and tool-specific requirements. The methodology permits for the verification of the platform description at different stages in the development process (i.e., HDL for simulation, static FPGA implementation, controller simulation and verification). Furthermore, automation capabilities embedded in the flow enable the generation of the platform description and the integration of the reconfiguration controller executive seamlessly. In order to demonstrate the benefits of the proposed approach, we present a case study in which we target the creation of an image-processing application to be deployed onto an FPGA board. We present the required modeling strategies and we discuss how the generation chains are integrated with the back-end Xilinx tools (the most mature version of PR technology) to produce the necessary executable artifacts: VHDL for the platform description and a C description of the reconfiguration controller to be executed by an embedded processor.<\/jats:p>","DOI":"10.1145\/2800784","type":"journal-article","created":{"date-parts":[[2015,12,4]],"date-time":"2015-12-04T13:43:07Z","timestamp":1449236587000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems"],"prefix":"10.1145","volume":"21","author":[{"given":"Gilberto","family":"Ochoa-Ruiz","sequence":"first","affiliation":[{"name":"Lab-STICC, Lorient, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S\u00e9bastien","family":"Guillet","sequence":"additional","affiliation":[{"name":"LIARA Laboratory, Qu\u00e9bec, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florent De","family":"Lamotte","sequence":"additional","affiliation":[{"name":"Lab-STICC, Lorient, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Rutten","sequence":"additional","affiliation":[{"name":"INRIA Rh\u00f4ne-Alpes, Grenoble, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"El-Bay","family":"Bourennane","sequence":"additional","affiliation":[{"name":"LE2I, Dijon, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Philippe","family":"Diguet","sequence":"additional","affiliation":[{"name":"Lab-STICC, Lorient, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guy","family":"Gogniat","sequence":"additional","affiliation":[{"name":"Lab-STICC, Lorient, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,2]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the Design, Automation, Test in Europe, Conference Exhibition","author":"Arpinen T.","year":"2009","unstructured":"T. Arpinen , T. Koskinen , E. Salminen , T. D. Hamalainen , and M. Hannikainen . 2009. Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA . In Proceedings of the Design, Automation, Test in Europe, Conference Exhibition , 2009 (DATE'09). 244--249. T. Arpinen, T. Koskinen, E. Salminen, T. D. Hamalainen, and M. Hannikainen. 2009. Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA. In Proceedings of the Design, Automation, Test in Europe, Conference Exhibition, 2009 (DATE'09). 244--249."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2436696.2443836"},{"volume-title":"ESL Models and Their Application","author":"Bailey Brian","key":"e_1_2_1_3_1","unstructured":"Brian Bailey and Grant Martin . 2010. IP meta-models for SoC assembly and HW\/SW interfaces . In ESL Models and Their Application , Springer US , 33--82. Brian Bailey and Grant Martin. 2010. IP meta-models for SoC assembly and HW\/SW interfaces. In ESL Models and Their Application, Springer US, 33--82."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2617597"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00454-4_10"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5381\/jot.2009.8.1.a1"},{"key":"e_1_2_1_7_1","unstructured":"CEA. 2014. Open Source Tool for Graphical UML2 Modelling. http:\/\/www.papyrusuml.org.  CEA. 2014. Open Source Tool for Graphical UML2 Modelling. http:\/\/www.papyrusuml.org."},{"key":"e_1_2_1_9_1","volume-title":"Proceedings of the 3rd International IEEE-NEWCAS Conference","author":"Dekeyser J.","year":"2005","unstructured":"J. Dekeyser , P. Boulet , P. Marquet , and S. Meftali . 2005. Model driven engineering for SoC co-design . In Proceedings of the 3rd International IEEE-NEWCAS Conference , 2005 . 21--25. J. Dekeyser, P. Boulet, P. Marquet, and S. Meftali. 2005. Model driven engineering for SoC co-design. In Proceedings of the 3rd International IEEE-NEWCAS Conference, 2005. 21--25."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1755951.1755898"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-13238-4_6"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368504"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2043662.2043663"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1155\/ES\/2006\/56320"},{"key":"e_1_2_1_15_1","doi-asserted-by":"crossref","unstructured":"Lingkan Gong and Oliver Diessel. 2014. Chapter 2: Verification challenges. In Functional Verification of Dynamically Reconfigurable FPGA-Based Systems Springer.  Lingkan Gong and Oliver Diessel. 2014. Chapter 2: Verification challenges. In Functional Verification of Dynamically Reconfigurable FPGA-Based Systems Springer.","DOI":"10.1007\/978-3-319-06838-1"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISORCW.2011.20"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339157"},{"key":"e_1_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629628"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.10.003"},{"key":"e_1_2_1_20_1","unstructured":"IEEE. 2009. IEEE 1685 IEEE Standard for IP-XACT Standard structure for packaging integrating and reusing IP within tools flows. http:\/\/standards.ieee.org\/getieee\/1685\/download\/1685-2009.pdf.  IEEE. 2009. IEEE 1685 IEEE Standard for IP-XACT Standard structure for packaging integrating and reusing IP within tools flows. http:\/\/standards.ieee.org\/getieee\/1685\/download\/1685-2009.pdf."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-014-0884-1"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the ARCS Workshops. 297--319","author":"Koch Dirk","year":"2012","unstructured":"Dirk Koch , Jim Torresen , Christian Beckhoff , Daniel Ziener , Christopher Dennl , Volker Breuer , J\u00fcrgen Teich , Michael Feilen , and Walter Stechele . 2012 . Partial reconfiguration on FPGAs in practice - Tools and applications . In Proceedings of the ARCS Workshops. 297--319 . Dirk Koch, Jim Torresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, J\u00fcrgen Teich, Michael Feilen, and Walter Stechele. 2012. Partial reconfiguration on FPGAs in practice - Tools and applications. In Proceedings of the ARCS Workshops. 297--319."},{"key":"e_1_2_1_23_1","doi-asserted-by":"crossref","unstructured":"S. Neuendorffer. 2010. Chapter 12: FPGA Platforms for Embedded Systems. In Model-Based Design for Embedded System Morgan Kaufmann.  S. Neuendorffer. 2010. Chapter 12: FPGA Platforms for Embedded Systems. In Model-Based Design for Embedded System Morgan Kaufmann.","DOI":"10.1201\/9781420067859-c12"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-012-9098-6"},{"key":"e_1_2_1_25_1","unstructured":"OMG. 2014a. Model-driven engineering. http:\/\/www.ogm\/org\/mda.  OMG. 2014a. Model-driven engineering. http:\/\/www.ogm\/org\/mda."},{"key":"e_1_2_1_26_1","unstructured":"OMG. 2014b. Modeling and analysis of real-time and embedded systems (MARTE) Beta 3. http:\/\/www.omgwiki.org\/marte-ftf2\/doku.php.  OMG. 2014b. Modeling and analysis of real-time and embedded systems (MARTE) Beta 3. http:\/\/www.omgwiki.org\/marte-ftf2\/doku.php."},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068722"},{"key":"e_1_2_1_28_1","unstructured":"Ponzet. 2006. Sim2Chro. Official website and user manual. http:\/\/www.di.ens.fr\/&sim;pouzet\/lucid-synchrone\/manual_html\/manual038.html.  Ponzet. 2006. Sim2Chro. Official website and user manual. http:\/\/www.di.ens.fr\/&sim;pouzet\/lucid-synchrone\/manual_html\/manual038.html."},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2012.01.001"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.21072"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.890107"},{"volume-title":"Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'09)","author":"Schattkowsky T.","key":"e_1_2_1_32_1","unstructured":"T. Schattkowsky , Tao Xie , and W. Mueller . 2009. A UML frontend for IP-XACT-based IP management . In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'09) , 238--243. T. Schattkowsky, Tao Xie, and W. Mueller. 2009. A UML frontend for IP-XACT-based IP management. In Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE'09), 238--243."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2006.58"},{"key":"e_1_2_1_34_1","unstructured":"Sodius. 2014. MDWorkbench Rererence Manual. http:\/\/www.sodius.org.  Sodius. 2014. MDWorkbench Rererence Manual. http:\/\/www.sodius.org."},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2012.07.004"},{"key":"e_1_2_1_36_1","volume-title":"Proceedings of the Design, Automation and Test in Europe (DATE","author":"Vidal J.","year":"2011","unstructured":"J. Vidal , F. de Lamotte , G. Gogniat , J.-P. Diguet and S. Guillet . 2011. Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation . In Proceedings of the Design, Automation and Test in Europe (DATE 2011 ). 1--4. J. Vidal, F. de Lamotte, G. Gogniat, J.-P. Diguet and S. Guillet. 2011. Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation. In Proceedings of the Design, Automation and Test in Europe (DATE 2011). 1--4."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-28365-9_2"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2012.6322884"},{"key":"e_1_2_1_39_1","unstructured":"Xilinx. 2012a. EDK concepts tools and techniques UG683. http:\/\/www.xilinx.com.  Xilinx. 2012a. EDK concepts tools and techniques UG683. http:\/\/www.xilinx.com."},{"key":"e_1_2_1_40_1","unstructured":"Xilinx. 2012b. Embedded System Tools Reference Manual EDK UG111. http:\/\/www.xilinx.com.  Xilinx. 2012b. Embedded System Tools Reference Manual EDK UG111. http:\/\/www.xilinx.com."},{"key":"e_1_2_1_41_1","unstructured":"Xilinx. 2012c. Partial reconfiguration overview WP374. http:\/\/www.xilinx.com.  Xilinx. 2012c. Partial reconfiguration overview WP374. http:\/\/www.xilinx.com."},{"key":"e_1_2_1_42_1","unstructured":"Xilinx. 2012d. Platform Specification Format Reference Manual 14.1 UG642. http:\/\/www.xilinx.com.  Xilinx. 2012d. Platform Specification Format Reference Manual 14.1 UG642. http:\/\/www.xilinx.com."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2800784","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2800784","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:42:44Z","timestamp":1750225364000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2800784"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12,2]]},"references-count":41,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2015,12,2]]}},"alternative-id":["10.1145\/2800784"],"URL":"https:\/\/doi.org\/10.1145\/2800784","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2015,12,2]]},"assertion":[{"value":"2014-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-06-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-12-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}