{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:49:09Z","timestamp":1759146549488,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,8,31]],"date-time":"2015-08-31T00:00:00Z","timestamp":1440979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,8,31]]},"DOI":"10.1145\/2800986.2801009","type":"proceedings-article","created":{"date-parts":[[2015,10,30]],"date-time":"2015-10-30T15:27:07Z","timestamp":1446218827000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["High PSRR Nano-Watt MOS-Only Threshold Voltage Monitor Circuit"],"prefix":"10.1145","author":[{"given":"Jhon A. Gomez","family":"C.","sequence":"first","affiliation":[{"name":"NSCAD Microeletr\u00f4nica, PGMicro - UFRGS, Porto Alegre, RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamilton","family":"Klimach","sequence":"additional","affiliation":[{"name":"Electrical Engineering Dept. UFRGS, Porto Alegre, RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Fabris","sequence":"additional","affiliation":[{"name":"NSCAD Microeletr\u00f4nica, Electrical Engineering Dept. UFRGS, Porto Alegre, RS, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oscar E.","family":"Mattia","sequence":"additional","affiliation":[{"name":"mmWave group, imec, ETRO, Vrij Universiteit Brussel, Brussel, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,8,31]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"CMOS Circuit Design, Layout, and Simulation","author":"Baker R. J.","year":"2004","unstructured":"R. J. Baker . CMOS Circuit Design, Layout, and Simulation , Second Edition. Wiley-IEEE Press , 2004 . R. J. Baker. CMOS Circuit Design, Layout, and Simulation, Second Edition. Wiley-IEEE Press, 2004."},{"issue":"2","key":"e_1_3_2_1_2_1","first-page":"61","article-title":"A 2-nw 1.1-v self-biased current reference in cmos technology. Circuits and Systems II: Express Briefs","volume":"52","author":"Camacho-Galeano E. M.","year":"2005","unstructured":"E. M. Camacho-Galeano , C. Galup-Montoro , and M. C. Schneider . A 2-nw 1.1-v self-biased current reference in cmos technology. Circuits and Systems II: Express Briefs , IEEE Transactions on , 52 ( 2 ): 61 -- 65 , Feb 2005 . E. M. Camacho-Galeano, C. Galup-Montoro, and M. C. Schneider. A 2-nw 1.1-v self-biased current reference in cmos technology. Circuits and Systems II: Express Briefs, IEEE Transactions on, 52(2):61--65, Feb 2005.","journal-title":"IEEE Transactions on"},{"issue":"5","key":"e_1_3_2_1_3_1","first-page":"1528","article-title":"An optimally self-biased threshold-voltage extractor {mosfet circuit parametric testing}. Instrumentation and Measurement","volume":"52","author":"\u00c7ilingiro\u011flu U.","year":"2003","unstructured":"U. \u00c7ilingiro\u011flu and S. K. Hoon . An optimally self-biased threshold-voltage extractor {mosfet circuit parametric testing}. Instrumentation and Measurement , IEEE Transactions on , 52 ( 5 ): 1528 -- 1532 , Oct 2003 . U. \u00c7ilingiro\u011flu and S. K. Hoon. An optimally self-biased threshold-voltage extractor {mosfet circuit parametric testing}. Instrumentation and Measurement, IEEE Transactions on, 52(5):1528--1532, Oct 2003.","journal-title":"IEEE Transactions on"},{"issue":"10","key":"e_1_3_2_1_4_1","first-page":"1510","article-title":"An mos transistor model for analog circuit design. Solid-State Circuits","volume":"33","author":"Cunha A.","year":"1998","unstructured":"A. Cunha , M. C. Schneider , and C. Galup-Montoro . An mos transistor model for analog circuit design. Solid-State Circuits , IEEE Journal of , 33 ( 10 ): 1510 -- 1519 , 1998 . A. Cunha, M. C. Schneider, and C. Galup-Montoro. An mos transistor model for analog circuit design. Solid-State Circuits, IEEE Journal of, 33(10):1510--1519, 1998.","journal-title":"IEEE Journal of"},{"issue":"6","key":"e_1_3_2_1_5_1","first-page":"626","article-title":"Low-voltage low-power accurate cmos vt extractor. Circuits and Systems II: Analog and Digital Signal Processing","volume":"48","author":"Fikos G.","year":"2001","unstructured":"G. Fikos and S. Siskos . Low-voltage low-power accurate cmos vt extractor. Circuits and Systems II: Analog and Digital Signal Processing , IEEE Transactions on , 48 ( 6 ): 626 -- 628 , Jun 2001 . G. Fikos and S. Siskos. Low-voltage low-power accurate cmos vt extractor. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 48(6):626--628, Jun 2001.","journal-title":"IEEE Transactions on"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:ALOG.0000011161.44537.da"},{"issue":"6","key":"e_1_3_2_1_7_1","first-page":"704","article-title":"An input-free vt extractor circuit using a two-transistor differential amplifier. Solid-State Circuits","volume":"28","author":"Johnson M.","year":"1993","unstructured":"M. Johnson . An input-free vt extractor circuit using a two-transistor differential amplifier. Solid-State Circuits , IEEE Journal of , 28 ( 6 ): 704 -- 705 , Jun 1993 . M. Johnson. An input-free vt extractor circuit using a two-transistor differential amplifier. Solid-State Circuits, IEEE Journal of, 28(6):704--705, Jun 1993.","journal-title":"IEEE Journal of"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2660540.2660991"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168679"},{"key":"e_1_3_2_1_10_1","first-page":"625","volume-title":"NSTI Nanotech","volume":"3","author":"Rossi C.","year":"2007","unstructured":"C. Rossi , C. Galup-Montoro , and M. C. Schneider . Ptat voltage generator based on an mos voltage divider . In NSTI Nanotech , volume 3 , pages 625 -- 628 , 2007 . C. Rossi, C. Galup-Montoro, and M. C. Schneider. Ptat voltage generator based on an mos voltage divider. In NSTI Nanotech, volume 3, pages 625--628, 2007."},{"key":"e_1_3_2_1_11_1","volume-title":"AN INPUT-FREE NMOS VT EXTRACTOR CIRCUIT IN PRESENCE OF BODY EFFECTS. In IEEE International Symposium on Circuits and Systems","author":"Sengupta S.","year":"2004","unstructured":"S. Sengupta . AN INPUT-FREE NMOS VT EXTRACTOR CIRCUIT IN PRESENCE OF BODY EFFECTS. In IEEE International Symposium on Circuits and Systems , 2004 . S. Sengupta. AN INPUT-FREE NMOS VT EXTRACTOR CIRCUIT IN PRESENCE OF BODY EFFECTS. In IEEE International Symposium on Circuits and Systems, 2004."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2012.01.004"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1049\/el:20070917"},{"key":"e_1_3_2_1_14_1","volume-title":"IEEE International Conference on Electronics, Circuits, and Systems, (3):282--285","author":"Wang Y.","year":"2004","unstructured":"Y. Wang , G. Tarr , and Y. Wang . Input-Free cascode Vthn and Vthp Extractor Circuits . IEEE International Conference on Electronics, Circuits, and Systems, (3):282--285 , 2004 . Y. Wang, G. Tarr, and Y. Wang. Input-Free cascode Vthn and Vthp Extractor Circuits. IEEE International Conference on Electronics, Circuits, and Systems, (3):282--285, 2004."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.149434"}],"event":{"name":"SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design","sponsor":["SBC Brazilian Computer Society","SIGDA ACM Special Interest Group on Design Automation","SBMICRO Brazilian Microelectronics Society"],"location":"Salvador Brazil","acronym":"SBCCI '15"},"container-title":["Proceedings of the 28th Symposium on Integrated Circuits and Systems Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2800986.2801009","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2800986.2801009","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:42:58Z","timestamp":1750225378000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2800986.2801009"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,8,31]]},"references-count":15,"alternative-id":["10.1145\/2800986.2801009","10.1145\/2800986"],"URL":"https:\/\/doi.org\/10.1145\/2800986.2801009","relation":{},"subject":[],"published":{"date-parts":[[2015,8,31]]},"assertion":[{"value":"2015-08-31","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}