{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:46:16Z","timestamp":1767339976310,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":36,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,11,24]],"date-time":"2015-11-24T00:00:00Z","timestamp":1448323200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,11,24]]},"DOI":"10.1145\/2814576.2814806","type":"proceedings-article","created":{"date-parts":[[2015,11,30]],"date-time":"2015-11-30T19:03:51Z","timestamp":1448910231000},"page":"37-49","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":74,"title":["Quartz"],"prefix":"10.1145","author":[{"given":"Haris","family":"Volos","sequence":"first","affiliation":[{"name":"Hewlett Packard Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guilherme","family":"Magalhaes","sequence":"additional","affiliation":[{"name":"Hewlett Packard Enterprise"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ludmila","family":"Cherkasova","sequence":"additional","affiliation":[{"name":"Hewlett Packard Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Li","sequence":"additional","affiliation":[{"name":"Hewlett Packard Labs"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,11,24]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Graph500. http:\/\/www.graph500.org\/.  Graph500. http:\/\/www.graph500.org\/."},{"key":"e_1_3_2_1_2_1","unstructured":"Intel 64 and ia-32 architectures optimization reference manual. http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/manuals\/64-ia-32-architectures-optimization-manual.pdf.  Intel 64 and ia-32 architectures optimization reference manual. http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/manuals\/64-ia-32-architectures-optimization-manual.pdf."},{"key":"e_1_3_2_1_3_1","unstructured":"Intel Architecture Instruction Set Extensions Programming Reference. https:\/\/software.intel.com\/sites\/default\/files\/managed\/0d\/53\/319433-022.pdf.  Intel Architecture Instruction Set Extensions Programming Reference. https:\/\/software.intel.com\/sites\/default\/files\/managed\/0d\/53\/319433-022.pdf."},{"key":"e_1_3_2_1_4_1","unstructured":"Intel Memory Latency Checker. https:\/\/software.intel.com\/en-us\/articles\/intelr-memory-latency-checker.  Intel Memory Latency Checker. https:\/\/software.intel.com\/en-us\/articles\/intelr-memory-latency-checker."},{"key":"e_1_3_2_1_5_1","unstructured":"Intel Memory Latency Checker v2.0 released. https:\/\/software.intel.com\/en-us\/forums\/topic\/517571.  Intel Memory Latency Checker v2.0 released. https:\/\/software.intel.com\/en-us\/forums\/topic\/517571."},{"key":"e_1_3_2_1_6_1","unstructured":"Intel xeon e5-product family. http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/datasheets\/xeon-e5-1600-2600-vol-2-datasheet.pdf.  Intel xeon e5-product family. http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/datasheets\/xeon-e5-1600-2600-vol-2-datasheet.pdf."},{"key":"e_1_3_2_1_7_1","unstructured":"Intel Xeon Processor E5-1600\/2400\/2600\/4600 (E5-Product Family.) http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/datasheets\/xeon-e5-1600-2600-vol-2-datasheet.pdf.  Intel Xeon Processor E5-1600\/2400\/2600\/4600 (E5-Product Family.) http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/datasheets\/xeon-e5-1600-2600-vol-2-datasheet.pdf."},{"key":"e_1_3_2_1_8_1","unstructured":"numactl - Control NUMA policy for processes or shared memory. http:\/\/linux.die.net\/man\/8\/numactl\/.  numactl - Control NUMA policy for processes or shared memory. http:\/\/linux.die.net\/man\/8\/numactl\/."},{"key":"e_1_3_2_1_9_1","unstructured":"PAPI\n  : Performance application programming interface. http:\/\/icl.cs.utk.edu\/papi\/.  PAPI: Performance application programming interface. http:\/\/icl.cs.utk.edu\/papi\/."},{"key":"e_1_3_2_1_10_1","unstructured":"PCMSIM\n  : A simple PCM block device simulator for linux. https:\/\/code.google.com\/p\/pcmsim\/.  PCMSIM: A simple PCM block device simulator for linux. https:\/\/code.google.com\/p\/pcmsim\/."},{"key":"e_1_3_2_1_11_1","unstructured":"perf: Linux profiling with performance counters. https:\/\/perf.wiki.kernel.org\/index.php\/Main_Page.  perf: Linux profiling with performance counters. https:\/\/perf.wiki.kernel.org\/index.php\/Main_Page."},{"key":"e_1_3_2_1_12_1","unstructured":"pmem.io: Persistent memory programming. http:\/\/pmem.io\/.  pmem.io: Persistent memory programming. http:\/\/pmem.io\/."},{"key":"e_1_3_2_1_13_1","unstructured":"SNIA NVM programming technical work group. http:\/\/www.snia.org\/forums\/sssi\/nvmp.  SNIA NVM programming technical work group. http:\/\/www.snia.org\/forums\/sssi\/nvmp."},{"key":"e_1_3_2_1_14_1","unstructured":"STREAM benchmark: http:\/\/www.cs.virginia.edu\/stream\/.  STREAM benchmark: http:\/\/www.cs.virginia.edu\/stream\/."},{"key":"e_1_3_2_1_15_1","unstructured":"Why Intel Added the CLWB and PCOMMIT Instructions. http:\/\/danluu.com\/clwb-pcommit\/.  Why Intel Added the CLWB and PCOMMIT Instructions. http:\/\/danluu.com\/clwb-pcommit\/."},{"key":"e_1_3_2_1_16_1","unstructured":"With The Machine HP May Have Invented a New Kind of Computer. http:\/\/www.businessweek.com\/articles\/2014-06-11\/with-the-machine-hp-may-have-invented-a-new-kind-of-computer.  With The Machine HP May Have Invented a New Kind of Computer. http:\/\/www.businessweek.com\/articles\/2014-06-11\/with-the-machine-hp-may-have-invented-a-new-kind-of-computer."},{"key":"e_1_3_2_1_17_1","volume-title":"FireBox: A Hardware Building Block for 2020 Warehouse-Scale Computers. In Proc. of FAST","author":"Asanovic K.","year":"2014","unstructured":"K. Asanovic . FireBox: A Hardware Building Block for 2020 Warehouse-Scale Computers. In Proc. of FAST , 2014 . K. Asanovic. FireBox: A Hardware Building Block for 2020 Warehouse-Scale Computers. In Proc. of FAST, 2014."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.33"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629589"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592814"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.65"},{"key":"e_1_3_2_1_23_1","volume-title":"YRL-2004-038, Yahoo! Research Labs","author":"Gleigh D.","year":"2004","unstructured":"D. Gleigh , L. Zhukov , and P. Berkhin . PageRank: A Linear System Approach. Technical report , YRL-2004-038, Yahoo! Research Labs , 2004 . D. Gleigh, L. Zhukov, and P. Berkhin. PageRank: A Linear System Approach. Technical report, YRL-2004-038, Yahoo! Research Labs, 2004."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-24322-6_20"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2168836.2168855"},{"key":"e_1_3_2_1_27_1","volume-title":"Proceedings of the 7th Biennial Conference on Innovative Data Systems Research (CIDR)","author":"Oukid I.","year":"2015","unstructured":"I. Oukid , W. Lehner , T. Kissinger , T. Willhalm , and P. Bumbulis . Instant recovery for main memory databases . In Proceedings of the 7th Biennial Conference on Innovative Data Systems Research (CIDR) , 2015 . I. Oukid, W. Lehner, T. Kissinger, T. Willhalm, and P. Bumbulis. Instant recovery for main memory databases. In Proceedings of the 7th Biennial Conference on Innovative Data Systems Research (CIDR), 2015."},{"key":"e_1_3_2_1_28_1","unstructured":"K. Packard. The Machine Architecture. http:\/\/keithp.com\/blogs\/the_machine_architecture.  K. Packard. The Machine Architecture. http:\/\/keithp.com\/blogs\/the_machine_architecture."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665712"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.14778\/2732228.2732231"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555760"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2668930.2695529"},{"key":"e_1_3_2_1_34_1","volume-title":"Proc. of Usenix ATC","author":"Su B.","year":"2014","unstructured":"B. Su , J. L. Greathouse , J. Gu , M. Boyer , and Z. Wang . Implementing a Leading Loads Performance Predictor on Commodity Processors . In Proc. of Usenix ATC , 2014 . B. Su, J. L. Greathouse, J. Gu, M. Boyer, and Z. Wang. Implementing a Leading Loads Performance Predictor on Commodity Processors. In Proc. of Usenix ATC, 2014."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592810"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"}],"event":{"name":"Middleware '15: 16th International Middleware Conference","sponsor":["ACM Association for Computing Machinery","USENIX Assoc USENIX Assoc","IFIP International Federation for Information Processing"],"location":"Vancouver BC Canada","acronym":"Middleware '15"},"container-title":["Proceedings of the 16th Annual Middleware Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2814576.2814806","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2814576.2814806","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:42Z","timestamp":1750225722000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2814576.2814806"}},"subtitle":["A Lightweight Performance Emulator for Persistent Memory Software"],"short-title":[],"issued":{"date-parts":[[2015,11,24]]},"references-count":36,"alternative-id":["10.1145\/2814576.2814806","10.1145\/2814576"],"URL":"https:\/\/doi.org\/10.1145\/2814576.2814806","relation":{},"subject":[],"published":{"date-parts":[[2015,11,24]]},"assertion":[{"value":"2015-11-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}