{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,16]],"date-time":"2026-01-16T00:34:12Z","timestamp":1768523652077,"version":"3.49.0"},"reference-count":7,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2015,9,13]],"date-time":"2015-09-13T00:00:00Z","timestamp":1442102400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2015,10]]},"abstract":"<jats:p>We present RIFFA 2.1, a reusable integration framework for Field-Programmable Gate Array (FPGA) accelerators. RIFFA provides communication and synchronization for FPGA accelerated applications using simple interfaces for hardware and software. Our goal is to expand the use of FPGAs as an acceleration platform by releasing, as open source, a framework that easily integrates software running on commodity CPUs with FPGA cores. RIFFA uses PCI Express (PCIe) links to connect FPGAs to a CPU\u2019s system bus. RIFFA 2.1 supports FPGAs from Xilinx and Altera, Linux and Windows operating systems, and allows multiple FPGAs to connect to a single host PC system. It has software bindings for C\/C++, Java, Python, and Matlab. Tests show that data transfers between hardware and software can reach 97% of the achievable PCIe link bandwidth.<\/jats:p>","DOI":"10.1145\/2815631","type":"journal-article","created":{"date-parts":[[2015,9,15]],"date-time":"2015-09-15T12:09:15Z","timestamp":1442318955000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":103,"title":["RIFFA 2.1"],"prefix":"10.1145","volume":"8","author":[{"given":"Matthew","family":"Jacobsen","sequence":"first","affiliation":[{"name":"University of California, San Diego, La Jolla, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dustin","family":"Richmond","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew","family":"Hogains","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, California"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryan","family":"Kastner","sequence":"additional","affiliation":[{"name":"University of California, San Diego, La Jolla, California"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,9,13]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"R. Brodersen A. Tkachenko and H. Kwok-Hay So. 2006. A unified hardware\/software runtime environment for FPGA-based reconfigurable computers using BORPH. In CODES+ISSS\u201906.  R. Brodersen A. Tkachenko and H. Kwok-Hay So. 2006. A unified hardware\/software runtime environment for FPGA-based reconfigurable computers using BORPH. In CODES+ISSS\u201906."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.29"},{"key":"e_1_2_1_3_1","volume-title":"White Paper: Xilinx Virtex-4 and Virtex-5 FPGAs","author":"Goldhammer A.","year":"2008","unstructured":"A. Goldhammer and J. Ayer , Jr . 2008 . Understanding performance of PCI express systems. White Paper: Xilinx Virtex-4 and Virtex-5 FPGAs (2008). A. Goldhammer and J. Ayer, Jr. 2008. Understanding performance of PCI express systems. White Paper: Xilinx Virtex-4 and Virtex-5 FPGAs (2008)."},{"key":"e_1_2_1_4_1","unstructured":"J. M III. 2009. Open Component Portability Infrastructure (OPENCPI).  J. M III. 2009. Open Component Portability Infrastructure (OPENCPI)."},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.44"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344703"},{"key":"e_1_2_1_7_1","volume-title":"Hthreads: A computational model for reconfigurable devices","author":"Peck W.","year":"2006","unstructured":"W. Peck , E. K. Anderson , J. Agron , J. Stevens , F. Baijot , and D. L. Andrews . 2006 . Hthreads: A computational model for reconfigurable devices . In FPL. IEEE , 1--4. W. Peck, E. K. Anderson, J. Agron, J. Stevens, F. Baijot, and D. L. Andrews. 2006. Hthreads: A computational model for reconfigurable devices. In FPL. IEEE, 1--4."}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2815631","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2815631","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:22Z","timestamp":1750225702000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2815631"}},"subtitle":["A Reusable Integration Framework for FPGA Accelerators"],"short-title":[],"issued":{"date-parts":[[2015,9,13]]},"references-count":7,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2015,10]]}},"alternative-id":["10.1145\/2815631"],"URL":"https:\/\/doi.org\/10.1145\/2815631","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,9,13]]},"assertion":[{"value":"2014-07-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-01-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2015-09-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}