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Code Optim."],"published-print":{"date-parts":[[2016,1,7]]},"abstract":"<jats:p>\n            This article proposes Probabilistic Replacement Policy (PRP), a novel replacement policy that evicts the line with\n            <jats:italic>minimum estimated hit probability under optimal replacement<\/jats:italic>\n            instead of the line with maximum expected reuse distance. The latter is optimal under the independent reference model of programs, which does not hold for last-level caches (LLC).\n          <\/jats:p>\n          <jats:p>PRP requires 7% and 2% metadata overheads in the cache and DRAM respectively. Using a sampling scheme makes DRAM overhead negligible, with minimal performance impact. Including detailed overhead modeling and equal cache areas, PRP outperforms SHiP, a state-of-the-art LLC replacement algorithm, by 4% for memory-intensive SPEC-CPU2006 benchmarks.<\/jats:p>","DOI":"10.1145\/2818374","type":"journal-article","created":{"date-parts":[[2015,10,20]],"date-time":"2015-10-20T09:28:08Z","timestamp":1445333288000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":16,"title":["Reuse Distance-Based Probabilistic Cache Replacement"],"prefix":"10.1145","volume":"12","author":[{"given":"Subhasis","family":"Das","sequence":"first","affiliation":[{"name":"Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tor M.","family":"Aamodt","sequence":"additional","affiliation":[{"name":"University of British Columbia, BC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"William J.","family":"Dally","sequence":"additional","affiliation":[{"name":"NVIDIA\/Stanford University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,10,19]]},"reference":[{"doi-asserted-by":"publisher","key":"e_1_2_2_1_1","DOI":"10.1145\/321623.321632"},{"doi-asserted-by":"publisher","key":"e_1_2_2_2_1","DOI":"10.1147\/sj.52.0078"},{"doi-asserted-by":"publisher","key":"e_1_2_2_3_1","DOI":"10.1145\/2749469.2750398"},{"key":"e_1_2_2_4_1","volume-title":"Technical Report RC-2301. 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In Proceedings of the 4th Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), co-located with ISCA. 28--36 . Aamer Jaleel, Robert S. Cohn, Chi-Keung Luk, and Bruce Jacob. 2008. CMP &dollar; im: A pin-based on-the-fly multi-core cache simulator. In Proceedings of the 4th Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), co-located with ISCA. 28--36."},{"doi-asserted-by":"publisher","key":"e_1_2_2_8_1","DOI":"10.1145\/1816038.1815971"},{"doi-asserted-by":"publisher","key":"e_1_2_2_9_1","DOI":"10.1145\/2540708.2540733"},{"key":"e_1_2_2_10_1","volume-title":"Proceedings of the 25th International Conference on Computer Design (ICCD\u201907)","author":"Keramidas G.","year":"2007","unstructured":"G. Keramidas , P. Petoumenos , and S. Kaxiras . 2007. Cache replacement based on reuse-distance prediction . In Proceedings of the 25th International Conference on Computer Design (ICCD\u201907) . 245--250. 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