{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T04:14:02Z","timestamp":1750306442462,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":23,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,9,25]],"date-time":"2015-09-25T00:00:00Z","timestamp":1443139200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,9,25]]},"DOI":"10.1145\/2818567.2818685","type":"proceedings-article","created":{"date-parts":[[2023,1,14]],"date-time":"2023-01-14T01:46:54Z","timestamp":1673660814000},"page":"419-423","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Reversible Comparator Circuit Using a New Reversible Gate"],"prefix":"10.1145","author":[{"given":"Gunajit","family":"Kalita","sequence":"first","affiliation":[{"name":"Dept. of CSE, Assam Engineering College, Jalukbari, Guwahati 781013, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Navajit","family":"Saikia","sequence":"additional","affiliation":[{"name":"Dept. of ETE, Assam Engineering College, Jalukbari, Guwahati 781013, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,9,25]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"3","volume":"1","author":"Abbasalizadeh S.","year":"2013","unstructured":"Abbasalizadeh , S. , Forouzandeh , B. and Aghababa , H. 4 Bit Comparator Design Based on Reversible Logic Gates. Lecture notes on Information Theory. 1 , 3 ( Sept 2013 ). Abbasalizadeh, S., Forouzandeh, B. and Aghababa, H. 4 Bit Comparator Design Based on Reversible Logic Gates. Lecture notes on Information Theory. 1, 3 (Sept 2013).","journal-title":"Information Theory."},{"key":"e_1_3_2_1_2_1","volume-title":"Proceedings of the 45th International Symposium on Multiple-Valued Logic","author":"Allahyari-Abhari A.","year":"2015","unstructured":"Allahyari-Abhari , A. , Wille , R. and Drechsler , R . An examination of the NCV-|v1> Quantum Library Based on Minimal Circuits . In Proceedings of the 45th International Symposium on Multiple-Valued Logic ( Waterloo, Canada , 2015 ). Allahyari-Abhari, A., Wille, R. and Drechsler, R. An examination of the NCV-|v1> Quantum Library Based on Minimal Circuits. In Proceedings of the 45th International Symposium on Multiple-Valued Logic (Waterloo, Canada, 2015)."},{"key":"e_1_3_2_1_3_1","first-page":"1","volume":"22","author":"Al-Rabadi A. N.","unstructured":"Al-Rabadi , A. N. Closed --System quantum logic network implementation of the viterbi algorithm. Facta Universitatis Ser. Elec. Energ. 22 , 1(April 2009), 1 -- 13 . Al-Rabadi, A. N. Closed--System quantum logic network implementation of the viterbi algorithm. Facta Universitatis Ser. Elec. Energ. 22, 1(April 2009), 1--13.","journal-title":"Facta Universitatis Ser. Elec. Energ."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.176.0525"},{"key":"e_1_3_2_1_5_1","first-page":"3457","volume":"52","author":"Barenco A.","year":"1995","unstructured":"Barenco , A. , Bennet , C. H. , Cleve , R. , DiVinchenzo , D. , Margolus , N. , Shor , P. , Sleator , T. , Smolin , J. and Weinfurter , H. Elementary gates for quantum computation. The American Physical Society. 52 ( March 1995 ), 3457 -- 3467 . Barenco, A., Bennet, C. H., Cleve, R., DiVinchenzo, D., Margolus, N., Shor, P., Sleator, T., Smolin, J. and Weinfurter, H. Elementary gates for quantum computation. The American Physical Society. 52 (March 1995), 3457--3467.","journal-title":"The American Physical Society."},{"key":"e_1_3_2_1_6_1","first-page":"7","author":"Dehghan B.","year":"2014","unstructured":"Dehghan , B. , Roozbeh , A. and Zare , J. Design of Low Power Comparator Using DG Gate. Circuits and Systems ( 2014 ), 7 -- 12 . Dehghan, B., Roozbeh, A. and Zare, J. Design of Low Power Comparator Using DG Gate. Circuits and Systems (2014), 7--12.","journal-title":"J. Design of Low Power Comparator Using DG Gate. Circuits and Systems ("},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF01857727"},{"key":"e_1_3_2_1_8_1","first-page":"11","volume":"11","author":"Feynman","year":"1985","unstructured":"Feynman , R. Quantum Mehcanical Computers. Optics News. 11 ( 1985 ), 11 -- 20 . Feynman, R. Quantum Mehcanical Computers. Optics News. 11(1985), 11--20.","journal-title":"Quantum Mehcanical Computers. Optics News."},{"key":"e_1_3_2_1_9_1","first-page":"3","volume":"3","author":"Garipelly R.","year":"2013","unstructured":"Garipelly , R. , Kiran , P. M. and Kumar A. S. A Review on Reversible Logic Gates and their Implementation. International Journal of Emerging Technology and And Advanced Engineering. 3 , 3 ( March 2013 ). Garipelly, R., Kiran, P. M. and Kumar A. S. A Review on Reversible Logic Gates and their Implementation. International Journal of Emerging Technology and And Advanced Engineering. 3, 3 (March 2013).","journal-title":"Implementation. International Journal of Emerging Technology and And Advanced Engineering."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996790"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.5555\/998681.1006740"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.53.0183"},{"key":"e_1_3_2_1_13_1","volume":"2","author":"Nagamani A. N.","unstructured":"Nagamani , A. N. , Jayashree , H. V. and Bhagyalakshmi , H. R. Novel low Power Comparator Design using Reversible Logic Gates. International Journal of Computer Science and Engineering. 2 , 4(Aug--Sep 2011). Nagamani, A. N., Jayashree, H. V. and Bhagyalakshmi, H. R. Novel low Power Comparator Design using Reversible Logic Gates. International Journal of Computer Science and Engineering. 2, 4(Aug--Sep 2011).","journal-title":"Reversible Logic Gates. International Journal of Computer Science and Engineering."},{"key":"e_1_3_2_1_14_1","volume-title":"B. Fault Tolerant Reversible Circuits. In Proc. of the 40th Asilomar Conf. Signals, systems and Computers.","author":"Parhami","year":"2006","unstructured":"Parhami , B. Fault Tolerant Reversible Circuits. In Proc. of the 40th Asilomar Conf. Signals, systems and Computers. ( Pacific Grooves, CA , October 2006 ). Parhami, B. Fault Tolerant Reversible Circuits. In Proc. of the 40th Asilomar Conf. Signals, systems and Computers. (Pacific Grooves, CA, October 2006)."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.32.3266"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.proeng.2012.01.943"},{"key":"e_1_3_2_1_17_1","volume":"55","author":"Rangaraju H. G.","unstructured":"Rangaraju , H. G. , Hedge , V. , Raja , K. B. and Murulidhara , K. N. Design and Optimization of n-bit Reversible Binary Comparator. International Journal of Computer Application. 55 , 18( Oct, 2012). Rangaraju, H. G., Hedge, V., Raja, K. B. and Murulidhara, K. N. Design and Optimization of n-bit Reversible Binary Comparator. International Journal of Computer Application. 55, 18( Oct, 2012).","journal-title":"Reversible Binary Comparator. International Journal of Computer Application."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228368"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674837"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2009.49"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2010.5697872"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Toffoli T. 1980. Reversible Computing. Tech Memo MIT\/CLS\/TM-151 MIT Lab for Computer Science.  Toffoli T. 1980. Reversible Computing. Tech Memo MIT\/CLS\/TM-151 MIT Lab for Computer Science.","DOI":"10.21236\/ADA082021"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.tcs.2004.12.026"}],"event":{"name":"ICCCT '15: Sixth International Conference on Computer and Communication Technology 2015","acronym":"ICCCT '15","location":"Allahabad India"},"container-title":["Proceedings of the Sixth International Conference on Computer and Communication Technology 2015"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2818567.2818685","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2818567.2818685","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:42:49Z","timestamp":1750225369000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2818567.2818685"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9,25]]},"references-count":23,"alternative-id":["10.1145\/2818567.2818685","10.1145\/2818567"],"URL":"https:\/\/doi.org\/10.1145\/2818567.2818685","relation":{},"subject":[],"published":{"date-parts":[[2015,9,25]]},"assertion":[{"value":"2015-09-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}