{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T01:15:28Z","timestamp":1767834928930,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,10,5]],"date-time":"2015-10-05T00:00:00Z","timestamp":1444003200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002809","name":"Generalitat de Catalunya","doi-asserted-by":"publisher","award":["2014-SGR-1272,2014-SGR-1051"],"award-info":[{"award-number":["2014-SGR-1272,2014-SGR-1051"]}],"id":[{"id":"10.13039\/501100002809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004963","name":"Seventh Framework Programme","doi-asserted-by":"publisher","award":["288777,610402"],"award-info":[{"award-number":["288777,610402"]}],"id":[{"id":"10.13039\/501100004963","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003329","name":"Ministerio de Econom\u00eda y Competitividad","doi-asserted-by":"publisher","award":["TIN2012-34557,SEV-2011-00067,SVP-2014-068501"],"award-info":[{"award-number":["TIN2012-34557,SEV-2011-00067,SVP-2014-068501"]}],"id":[{"id":"10.13039\/501100003329","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,10,5]]},"DOI":"10.1145\/2818950.2818955","type":"proceedings-article","created":{"date-parts":[[2015,10,27]],"date-time":"2015-10-27T12:37:04Z","timestamp":1445949424000},"page":"31-36","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":33,"title":["Another Trip to the Wall"],"prefix":"10.1145","author":[{"given":"Milan","family":"Radulovic","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center (BSC), Universitat Polit\u00e8cnica de Catalunya (UPC), Barcelona, Spain"}]},{"given":"Darko","family":"Zivanovic","sequence":"additional","affiliation":[{"name":"BSC & UPC, Barcelona, Spain"}]},{"given":"Daniel","family":"Ruiz","sequence":"additional","affiliation":[{"name":"BSC, Barcelona, Spain"}]},{"given":"Bronis R.","family":"de Supinski","sequence":"additional","affiliation":[{"name":"Lawrence Livermore National Laboratory, Livermore, California"}]},{"given":"Sally A.","family":"McKee","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}]},{"given":"Petar","family":"Radojkovi\u0107","sequence":"additional","affiliation":[{"name":"BSC, Barcelona, Spain"}]},{"given":"Eduard","family":"Ayguad\u00e9","sequence":"additional","affiliation":[{"name":"BSC & UPC, Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2015,10,5]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Nov.","year":"2014","unstructured":"TOP500 List. http:\/\/www.top500.org\/ , Nov. 2014 . TOP500 List. http:\/\/www.top500.org\/, Nov. 2014."},{"key":"e_1_3_2_1_2_1","unstructured":"Arira Design. Hybrid Memory Cube Evaluation & Development Board. http:\/\/www.ariradesign.com\/hmc-board 2013.  Arira Design. Hybrid Memory Cube Evaluation & Development Board. http:\/\/www.ariradesign.com\/hmc-board 2013."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.641593"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597663"},{"issue":"5","key":"e_1_3_2_1_6_1","first-page":"1","volume":"13","author":"Diefendorff K.","year":"1999","unstructured":"K. Diefendorff . Sony's Emotionally Charged Chip . Microprocessor Report , 13 ( 5 ): 1 ,6--11, Apr. 1999 . K. Diefendorff. Sony's Emotionally Charged Chip. Microprocessor Report, 13(5):1,6--11, Apr. 1999.","journal-title":"Microprocessor Report"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/77626.79170"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2014.15"},{"key":"e_1_3_2_1_9_1","volume-title":"International Conference on Architectural Support for Programming Languages and Operating Systems, Wild and Crazy Ideas Session","author":"Glew A.","year":"1998","unstructured":"A. Glew . MLP yes! ILP no! International Conference on Architectural Support for Programming Languages and Operating Systems, Wild and Crazy Ideas Session , Oct. 1998 . A. Glew. MLP yes! ILP no! International Conference on Architectural Support for Programming Languages and Operating Systems, Wild and Crazy Ideas Session, Oct. 1998."},{"key":"e_1_3_2_1_10_1","volume-title":"4th Generation Intel\u00ae Core\u2122Processor, co-denamed Haswell. Hot Chips","author":"Hammarlund P.","year":"2013","unstructured":"P. Hammarlund . 4th Generation Intel\u00ae Core\u2122Processor, co-denamed Haswell. Hot Chips 25, Aug. 2013 . P. Hammarlund. 4th Generation Intel\u00ae Core\u2122Processor, co-denamed Haswell. Hot Chips 25, Aug. 2013."},{"key":"e_1_3_2_1_11_1","volume-title":"Nov.","author":"Hybrid Memory Cube Consortium","year":"2014","unstructured":"Hybrid Memory Cube Consortium . Hybrid Memory Cube Specification 2.0. www.hybridmemorycube.org\/specification-v2-download-form\/ , Nov. 2014 . Hybrid Memory Cube Consortium. Hybrid Memory Cube Specification 2.0. www.hybridmemorycube.org\/specification-v2-download-form\/, Nov. 2014."},{"key":"e_1_3_2_1_12_1","volume-title":"Intel\u00ae Pentium\u00ae 4 Processor and Intel\u00ae E7205 Chipset Design Guide","author":"Intel Corporation","year":"2002","unstructured":"Intel Corporation . Intel\u00ae Pentium\u00ae 4 Processor and Intel\u00ae E7205 Chipset Design Guide . Dec. 2002 . Intel Corporation. Intel\u00ae Pentium\u00ae 4 Processor and Intel\u00ae E7205 Chipset Design Guide. Dec. 2002."},{"key":"e_1_3_2_1_13_1","volume-title":"Intel\u00ae 875P Chipset Datasheet","author":"Intel Corporation","year":"2004","unstructured":"Intel Corporation . Intel\u00ae 875P Chipset Datasheet . Feb. 2004 . Intel Corporation. Intel\u00ae 875P Chipset Datasheet. Feb. 2004."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/1855094"},{"key":"e_1_3_2_1_15_1","volume-title":"Measurement, Simulation, and Modeling","author":"Jain R.","year":"1991","unstructured":"R. Jain . The Art of Computer Systems Performance Analysis: Techniques for Experimental Design , Measurement, Simulation, and Modeling . Wiley , Apr. 1991 . R. Jain. The Art of Computer Systems Performance Analysis: Techniques for Experimental Design, Measurement, Simulation, and Modeling. Wiley, Apr. 1991."},{"key":"e_1_3_2_1_16_1","volume-title":"Feb.","author":"JEDEC Solid State Technology Association","year":"2008","unstructured":"JEDEC Solid State Technology Association . Double Data Rate (DDR) SDRAM Standard. www.jedec.org\/standards-documents\/docs\/jesd-79f , Feb. 2008 . JEDEC Solid State Technology Association. Double Data Rate (DDR) SDRAM Standard. www.jedec.org\/standards-documents\/docs\/jesd-79f, Feb. 2008."},{"key":"e_1_3_2_1_17_1","volume-title":"Oct.","author":"JEDEC Solid State Technology Association","year":"2013","unstructured":"JEDEC Solid State Technology Association . High Bandwidth Memory (HBM) DRAM. www.jedec.org\/standards-documents\/docs\/jesd235 , Oct. 2013 . JEDEC Solid State Technology Association. High Bandwidth Memory (HBM) DRAM. www.jedec.org\/standards-documents\/docs\/jesd235, Oct. 2013."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.38"},{"key":"e_1_3_2_1_19_1","volume-title":"Jan.","author":"Mandapati A.","year":"2002","unstructured":"A. Mandapati . 2001: A Graphics Odyssey. Microprocessor Report, 16(1):7--10 , Jan. 2002 . A. Mandapati. 2001: A Graphics Odyssey. Microprocessor Report, 16(1):7--10, Jan. 2002."},{"key":"e_1_3_2_1_20_1","first-page":"19","volume-title":"IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter","author":"McCalpin J. D.","year":"1995","unstructured":"J. D. McCalpin . Memory Bandwidth and Machine Balance in Current High Performance Computers . IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter , pages 19 -- 25 , Dec. 1995 . J. D. McCalpin. Memory Bandwidth and Machine Balance in Current High Performance Computers. IEEE Computer Society Technical Committee on Computer Architecture (TCCA) Newsletter, pages 19--25, Dec. 1995."},{"key":"e_1_3_2_1_21_1","volume-title":"Sustainable Memory Bandwidth in High Performance Computers. https:\/\/www.cs.virginia.edu\/stream\/ref.html","author":"McCalpin J. D.","year":"1997","unstructured":"J. D. McCalpin . STREAM : Sustainable Memory Bandwidth in High Performance Computers. https:\/\/www.cs.virginia.edu\/stream\/ref.html , 1997 . J. D. McCalpin. STREAM: Sustainable Memory Bandwidth in High Performance Computers. https:\/\/www.cs.virginia.edu\/stream\/ref.html, 1997."},{"key":"e_1_3_2_1_22_1","first-page":"247","volume-title":"USENIX Summer Conference","author":"Ousterhout J. K.","year":"1990","unstructured":"J. K. Ousterhout . Why Aren't Operating Systems Getting Faster As Fast as Hardware? USENIX Summer Conference , pages 247 -- 256 , June 1990 . J. K. Ousterhout. Why Aren't Operating Systems Getting Faster As Fast as Hardware? USENIX Summer Conference, pages 247--256, June 1990."},{"key":"e_1_3_2_1_23_1","volume-title":"Unified european applications benchmark suite. www.praceri.eu\/ueabs\/","author":"Advanced Partnership","year":"2013","unstructured":"Partnership for Advanced Computing in Europe (PRACE). Unified european applications benchmark suite. www.praceri.eu\/ueabs\/ , 2013 . Partnership for Advanced Computing in Europe (PRACE). Unified european applications benchmark suite. www.praceri.eu\/ueabs\/, 2013."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"e_1_3_2_1_25_1","unstructured":"A. Petitet R. C. Whaley J. Dongarra and A. Cleary. HPL - A Portable Implementation of the High-Performance Linpack Benchmark for Distributed-Memory Computers. http:\/\/www.netlib.org\/benchmark\/hpl\/ Sept. 2008.  A. Petitet R. C. Whaley J. Dongarra and A. Cleary. HPL - A Portable Implementation of the High-Performance Linpack Benchmark for Distributed-Memory Computers. http:\/\/www.netlib.org\/benchmark\/hpl\/ Sept. 2008."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"}],"event":{"name":"MEMSYS '15: International Symposium on Memory Systems","location":"Washington DC DC USA","acronym":"MEMSYS '15"},"container-title":["Proceedings of the 2015 International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2818950.2818955","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2818950.2818955","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:07:17Z","timestamp":1750223237000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2818950.2818955"}},"subtitle":["How Much Will Stacked DRAM Benefit HPC?"],"short-title":[],"issued":{"date-parts":[[2015,10,5]]},"references-count":26,"alternative-id":["10.1145\/2818950.2818955","10.1145\/2818950"],"URL":"https:\/\/doi.org\/10.1145\/2818950.2818955","relation":{},"subject":[],"published":{"date-parts":[[2015,10,5]]},"assertion":[{"value":"2015-10-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}