{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,21]],"date-time":"2026-04-21T23:27:32Z","timestamp":1776814052265,"version":"3.51.2"},"publisher-location":"New York, NY, USA","reference-count":49,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,10,5]],"date-time":"2015-10-05T00:00:00Z","timestamp":1444003200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100006435","name":"National Science Foundation","doi-asserted-by":"publisher","award":["#1205618, #1213052, #1302225, #1302557, #1317560, #1320478, #1409095, #1439021, and #1439057."],"award-info":[{"award-number":["#1205618, #1213052, #1302225, #1302557, #1317560, #1320478, #1409095, #1439021, and #1439057."]}],"id":[{"id":"10.13039\/100006435","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,10,5]]},"DOI":"10.1145\/2818950.2818979","type":"proceedings-article","created":{"date-parts":[[2015,10,27]],"date-time":"2015-10-27T12:37:04Z","timestamp":1445949424000},"page":"223-234","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":77,"title":["Anatomy of GPU Memory System for Multi-Application Execution"],"prefix":"10.1145","author":[{"given":"Adwait","family":"Jog","sequence":"first","affiliation":[{"name":"College of William and Mary"}]},{"given":"Onur","family":"Kayiran","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc."}]},{"given":"Tuba","family":"Kesten","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]},{"given":"Ashutosh","family":"Pattnaik","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]},{"given":"Evgeny","family":"Bolotin","sequence":"additional","affiliation":[{"name":"NVIDIA"}]},{"given":"Niladrish","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"NVIDIA"}]},{"given":"Stephen W.","family":"Keckler","sequence":"additional","affiliation":[{"name":"NVIDIA and University of Texas at Austin"}]},{"given":"Mahmut T.","family":"Kandemir","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[{"name":"Pennsylvania State University"}]}],"member":"320","published-online":{"date-parts":[[2015,10,5]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"JILP Workshop on Computer Architecture Competitions (Memory Scheduling Championship). http:\/\/www.cs.utah.edu\/~rajeev\/jwac12\/.","unstructured":"3rd JILP Workshop on Computer Architecture Competitions (Memory Scheduling Championship). http:\/\/www.cs.utah.edu\/~rajeev\/jwac12\/. 3rd JILP Workshop on Computer Architecture Competitions (Memory Scheduling Championship). http:\/\/www.cs.utah.edu\/~rajeev\/jwac12\/."},{"key":"e_1_3_2_1_2_1","unstructured":"AMD Radeon R9 290X. http:\/\/www.amd.com\/us\/press-releases\/Pages\/amd-radeon-r9-290x-2013oct24.aspx.  AMD Radeon R9 290X. http:\/\/www.amd.com\/us\/press-releases\/Pages\/amd-radeon-r9-290x-2013oct24.aspx."},{"key":"e_1_3_2_1_3_1","unstructured":"NVIDIA GRID. http:\/\/www.nvidia.com\/object\/grid-boards.html.  NVIDIA GRID. http:\/\/www.nvidia.com\/object\/grid-boards.html."},{"key":"e_1_3_2_1_4_1","unstructured":"NVIDIA GTX 780-Ti. http:\/\/www.nvidia.com\/gtx-700-graphics-cards\/gtx-780ti\/.  NVIDIA GTX 780-Ti. http:\/\/www.nvidia.com\/gtx-700-graphics-cards\/gtx-780ti\/."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168946"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2654822.2541956"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974717"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742976"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337207"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2014.16"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1735688.1735702"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815976"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155663"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485930"},{"key":"e_1_3_2_1_17_1","unstructured":"GPGPU-Sim v3.2.1. Address mapping.  GPGPU-Sim v3.2.1. Address mapping."},{"key":"e_1_3_2_1_18_1","unstructured":"GPGPU-Sim v3.2.1. GTX 480 Configuration.  GPGPU-Sim v3.2.1. GTX 480 Configuration."},{"key":"e_1_3_2_1_19_1","volume-title":"HotPar","author":"Gregg C.","year":"2012","unstructured":"C. Gregg , J. Dorn , K. Hazelwood , and K. Skadron . Fine-grained resource sharing for concurrent GPGPU kernels . In HotPar , 2012 . C. Gregg, J. Dorn, K. Hazelwood, and K. Skadron. Fine-grained resource sharing for concurrent GPGPU kernels. In HotPar, 2012."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.4"},{"key":"e_1_3_2_1_21_1","unstructured":"Hynix. Hynix GDDR5 SGRAM Part H5GQ1H24AFR Revision 1.0.  Hynix. Hynix GDDR5 SGRAM Part H5GQ1H24AFR Revision 1.0."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228513"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2304576.2304582"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2576779.2576780"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485951"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2499368.2451158"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.115"},{"key":"e_1_3_2_1_28_1","volume-title":"PACT","author":"Kayiran O.","year":"2013","unstructured":"O. Kayiran , A. Jog , M. T. Kandemir , and C. R. Das . Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs . In PACT , 2013 . O. Kayiran, A. Jog, M. T. Kandemir, and C. R. Das. Neither More Nor Less: Optimizing Thread-level Parallelism for GPGPUs. In PACT, 2013."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.62"},{"key":"e_1_3_2_1_30_1","volume-title":"HPCA","author":"Kim Y.","year":"2010","unstructured":"Y. Kim , D. Han , O. Mutlu , and M. Harchol-Balter . ATLAS: A Scalable and High-performance Scheduling Algorithm for Multiple Memory Controllers . In HPCA , 2010 . Y. Kim, D. Han, O. Mutlu, and M. Harchol-Balter. ATLAS: A Scalable and High-performance Scheduling Algorithm for Multiple Memory Controllers. In HPCA, 2010."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.32"},{"key":"e_1_3_2_1_33_1","volume-title":"Proc. WDDD","author":"Lin X.","year":"2011","unstructured":"X. Lin and R. Balasubramonian . Refining the utility metric for utility-based cache partitioning . Proc. WDDD , 2011 . X. Lin and R. Balasubramonian. Refining the utility metric for utility-based cache partitioning. Proc. WDDD, 2011."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382128"},{"key":"e_1_3_2_1_36_1","unstructured":"NVIDIA. CUDA C\/C++ SDK Code Samples 2011.  NVIDIA. CUDA C\/C++ SDK Code Samples 2011."},{"key":"e_1_3_2_1_37_1","volume-title":"Fermi: NVIDIA's Next Generation CUDA Compute Architecture","author":"NVIDIA.","year":"2011","unstructured":"NVIDIA. Fermi: NVIDIA's Next Generation CUDA Compute Architecture , 2011 . NVIDIA. Fermi: NVIDIA's Next Generation CUDA Compute Architecture, 2011."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2499368.2451160"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.22"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339668"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.16"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540718"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522356"},{"key":"e_1_3_2_1_46_1","volume-title":"ISCA","author":"Vijaykumar N.","year":"2015","unstructured":"N. Vijaykumar , G. Pekhimenko , A. Jog , A. Bhowmick , O. Mutlu , C. Das , M. T. Kandemir , T. Mowry , and R. Ausavarungnirun . Enabling Efficient Data Compression in GPUs . In ISCA , 2015 . N. Vijaykumar, G. Pekhimenko, A. Jog, A. Bhowmick, O. Mutlu, C. Das, M. T. Kandemir, T. Mowry, and R. Ausavarungnirun. Enabling Efficient Data Compression in GPUs. In ISCA, 2015."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592002"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSim.2011.5999803"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669119"},{"key":"e_1_3_2_1_50_1","first-page":"630","article-title":"Controller for a Synchronous DRAM that Maximizes Throughput by Allowing Memory Requests and Commands to be Issued Out of Order. (U.","volume":"5","author":"Zuravleff W. K.","year":"1997","unstructured":"W. K. Zuravleff and T. Robinson . Controller for a Synchronous DRAM that Maximizes Throughput by Allowing Memory Requests and Commands to be Issued Out of Order. (U. S. Patent Number 5 , 630 ,096), Sept. 1997 . W. K. Zuravleff and T. Robinson. Controller for a Synchronous DRAM that Maximizes Throughput by Allowing Memory Requests and Commands to be Issued Out of Order. (U.S. Patent Number 5,630,096), Sept. 1997.","journal-title":"S. Patent Number"}],"event":{"name":"MEMSYS '15: International Symposium on Memory Systems","location":"Washington DC DC USA","acronym":"MEMSYS '15"},"container-title":["Proceedings of the 2015 International Symposium on Memory Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2818950.2818979","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2818950.2818979","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:07:17Z","timestamp":1750223237000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2818950.2818979"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10,5]]},"references-count":49,"alternative-id":["10.1145\/2818950.2818979","10.1145\/2818950"],"URL":"https:\/\/doi.org\/10.1145\/2818950.2818979","relation":{},"subject":[],"published":{"date-parts":[[2015,10,5]]},"assertion":[{"value":"2015-10-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}