{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T08:43:42Z","timestamp":1774428222740,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,12,5]],"date-time":"2015-12-05T00:00:00Z","timestamp":1449273600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1253700"],"award-info":[{"award-number":["1253700"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,12,5]]},"DOI":"10.1145\/2830772.2830773","type":"proceedings-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T13:38:13Z","timestamp":1452519493000},"page":"1-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":94,"title":["Large pages and lightweight memory management in virtualized environments"],"prefix":"10.1145","author":[{"given":"Binh","family":"Pham","sequence":"first","affiliation":[{"name":"Rutgers University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J\u00e1n","family":"Vesel\u00fd","sequence":"additional","affiliation":[{"name":"Rutgers University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriel H.","family":"Loh","sequence":"additional","affiliation":[{"name":"Advanced Micro Devices, Inc."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abhishek","family":"Bhattacharjee","sequence":"additional","affiliation":[{"name":"Rutgers University"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,5]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"Software Optimization Guide for AMD Family 15h Processors \" Advanced Micro Devices Inc Tech. Rep. 2014.  \"Software Optimization Guide for AMD Family 15h Processors \" Advanced Micro Devices Inc Tech. Rep. 2014."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165153"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2005.1430554"},{"key":"e_1_3_2_1_4_1","unstructured":"A. Arcangeli \"Transparent Hugepage Support \" KVM Forum 2010.  A. Arcangeli \"Transparent Hugepage Support \" KVM Forum 2010."},{"key":"e_1_3_2_1_5_1","volume-title":"Increasing Memory Density by Using KSM,\" Ottawa Linux Symposium","author":"Arcangeli A.","year":"2009","unstructured":"A. Arcangeli , I. Eidus , and C. Wright , \" Increasing Memory Density by Using KSM,\" Ottawa Linux Symposium , 2009 . A. Arcangeli, I. Eidus, and C. Wright, \"Increasing Memory Density by Using KSM,\" Ottawa Linux Symposium, 2009."},{"key":"e_1_3_2_1_6_1","unstructured":"G. Atwood \"Current and Emerging Memory Technology Landscape \" Flash Memory Summit 2011.  G. Atwood \"Current and Emerging Memory Technology Landscape \" Flash Memory Summit 2011."},{"key":"e_1_3_2_1_7_1","article-title":"Memory Overcommittment in the ESX Server","author":"Banerjee I.","year":"2013","unstructured":"I. Banerjee , F. Guo , K. Tati , and R. Venkatasubramanian , \" Memory Overcommittment in the ESX Server ,\" VMware Technical Journal , 2013 . I. Banerjee, F. Guo, K. Tati, and R. Venkatasubramanian, \"Memory Overcommittment in the ESX Server,\" VMware Technical Journal, 2013.","journal-title":"VMware Technical Journal"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815970"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000101"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485943"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346286"},{"key":"e_1_3_2_1_12_1","volume-title":"Shared Last-Level TLBs for Chip Multiprocessors,\" HPCA","author":"Bhattacharjee A.","year":"2011","unstructured":"A. Bhattacharjee , D. Lustig , and M. Martonosi , \" Shared Last-Level TLBs for Chip Multiprocessors,\" HPCA , 2011 . A. Bhattacharjee, D. Lustig, and M. Martonosi, \"Shared Last-Level TLBs for Chip Multiprocessors,\" HPCA, 2011."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540741"},{"key":"e_1_3_2_1_14_1","volume-title":"The PARSEC Benchmark Suite: Characterization and Architectural Simplications,\" IISWC","author":"Bienia C.","year":"2008","unstructured":"C. Bienia , S. Kumar , J. P. Singh , and K. Li , \" The PARSEC Benchmark Suite: Characterization and Architectural Simplications,\" IISWC , 2008 . C. Bienia, S. Kumar, J. P. Singh, and K. Li, \"The PARSEC Benchmark Suite: Characterization and Architectural Simplications,\" IISWC, 2008."},{"key":"e_1_3_2_1_15_1","article-title":"Methodology for Performance Analysis of VMware vSphere under Tier-1 Applications","author":"Buell J.","year":"2013","unstructured":"J. Buell , D. Hecht , J. Heo , K. Saladi , and R. Taheri , \" Methodology for Performance Analysis of VMware vSphere under Tier-1 Applications ,\" VMWare Technical Journal , 2013 . J. Buell, D. Hecht, J. Heo, K. Saladi, and R. Taheri, \"Methodology for Performance Analysis of VMware vSphere under Tier-1 Applications,\" VMWare Technical Journal, 2013.","journal-title":"VMWare Technical Journal"},{"key":"e_1_3_2_1_16_1","volume-title":"Supporting Superpages in Non-Contiguous Physical Memory,\" HPCA","author":"Du Y.","year":"2015","unstructured":"Y. Du , M. Zhou , B. Childers , D. Mosse , and R. Melhem , \" Supporting Superpages in Non-Contiguous Physical Memory,\" HPCA , 2015 . Y. Du, M. Zhou, B. Childers, D. Mosse, and R. Melhem, \"Supporting Superpages in Non-Contiguous Physical Memory,\" HPCA, 2015."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.37"},{"key":"e_1_3_2_1_19_1","volume-title":"Large Pages May be Harmful on NUMA Systems,\" USENIX ATC","author":"Gaud F.","year":"2014","unstructured":"F. Gaud , B. Lepers , J. Decouchant , J. Funston , and A. Fedorova , \" Large Pages May be Harmful on NUMA Systems,\" USENIX ATC , 2014 . F. Gaud, B. Lepers, J. Decouchant, J. Funston, and A. Fedorova, \"Large Pages May be Harmful on NUMA Systems,\" USENIX ATC, 2014."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2731186.2731187"},{"key":"e_1_3_2_1_21_1","unstructured":"D. Kanter \"Haswell Memory Hierarchy \" http:\/\/www.realworldtech.com\/haswell-cpu\/5\/ 2012.  D. Kanter \"Haswell Memory Hierarchy \" http:\/\/www.realworldtech.com\/haswell-cpu\/5\/ 2012."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749471"},{"key":"e_1_3_2_1_23_1","unstructured":"B. Kero \"Running 512 Containers on a Laptop \" http:\/\/bke.ro\/running-512-containers-on-a-laptop 2015.  B. Kero \"Running 512 Containers on a Laptop \" http:\/\/bke.ro\/running-512-containers-on-a-laptop 2015."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_25_1","volume-title":"Heterogeneous Memory Architectures: A HW\/SW Approach for Mixing Die-Stacked and Off-Package Memories,\" HPCA","author":"Meswani M.","year":"2015","unstructured":"M. Meswani , S. Blagodurov , D. Roberts , J. Slice , M. Ignatowski , and G. Loh , \" Heterogeneous Memory Architectures: A HW\/SW Approach for Mixing Die-Stacked and Off-Package Memories,\" HPCA , 2015 . M. Meswani, S. Blagodurov, D. Roberts, J. Slice, M. Ignatowski, and G. Loh, \"Heterogeneous Memory Architectures: A HW\/SW Approach for Mixing Die-Stacked and Off-Package Memories,\" HPCA, 2015."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1060289.1060299"},{"key":"e_1_3_2_1_27_1","volume-title":"Prediction-Based Superpage-Friendly TLB Designs,\" HPCA","author":"Papadopoulou M.","year":"2014","unstructured":"M. Papadopoulou , X. Tong , A. Seznec , and A. Moshovos , \" Prediction-Based Superpage-Friendly TLB Designs,\" HPCA , 2014 . M. Papadopoulou, X. Tong, A. Seznec, and A. Moshovos, \"Prediction-Based Superpage-Friendly TLB Designs,\" HPCA, 2014."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.28"},{"key":"e_1_3_2_1_29_1","volume-title":"MLP Aware Heterogeneous Memory System,\" DATE","author":"Phadke S.","year":"2011","unstructured":"S. Phadke and S. Narayanasamy , \" MLP Aware Heterogeneous Memory System,\" DATE , 2011 . S. Phadke and S. Narayanasamy, \"MLP Aware Heterogeneous Memory System,\" DATE, 2011."},{"key":"e_1_3_2_1_30_1","volume-title":"Increasing TLB Reach by Exploiting Clustering in Page Translations,\" HPCA","author":"Pham B.","year":"2014","unstructured":"B. Pham , A. Bhattacharjee , Y. Eckert , and G. Loh , \" Increasing TLB Reach by Exploiting Clustering in Page Translations,\" HPCA , 2014 . B. Pham, A. Bhattacharjee, Y. Eckert, and G. Loh, \"Increasing TLB Reach by Exploiting Clustering in Page Translations,\" HPCA, 2014."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.32"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736057"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.20"},{"key":"e_1_3_2_1_34_1","unstructured":"A. W. Services \"AWS Cloud Formation User Guide \" 2010.  A. W. Services \"AWS Cloud Formation User Guide \" 2010."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/165123.165152"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.21"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195531"},{"key":"e_1_3_2_1_39_1","volume-title":"ESX Server 3.5 and ESX Server 3i v3.5,\" VMware Performance Study","author":"Performance Large Page","year":"2008","unstructured":"VMware, \" Large Page Performance : ESX Server 3.5 and ESX Server 3i v3.5,\" VMware Performance Study , 2008 . VMware, \"Large Page Performance: ESX Server 3.5 and ESX Server 3i v3.5,\" VMware Performance Study, 2008."},{"key":"e_1_3_2_1_40_1","unstructured":"VMware \"VProbes Programming Reference \" 2008.  VMware \"VProbes Programming Reference \" 2008."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1060289.1060307"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508293.1508299"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2013.6575349"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.20"}],"event":{"name":"MICRO-48: The 48th Annual IEEE\/ACM International Symposium of Microarchitecture","location":"Waikiki Hawaii","acronym":"MICRO-48","sponsor":["IEEE Computer Society TC-uARCH","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 48th International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830773","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830773","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:39Z","timestamp":1750225719000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830773"}},"subtitle":["can you have it both ways?"],"short-title":[],"issued":{"date-parts":[[2015,12,5]]},"references-count":43,"alternative-id":["10.1145\/2830772.2830773","10.1145\/2830772"],"URL":"https:\/\/doi.org\/10.1145\/2830772.2830773","relation":{},"subject":[],"published":{"date-parts":[[2015,12,5]]},"assertion":[{"value":"2015-12-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}