{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,20]],"date-time":"2026-01-20T05:28:21Z","timestamp":1768886901534,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,12,5]],"date-time":"2015-12-05T00:00:00Z","timestamp":1449273600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/H005633,EP\/K008528"],"award-info":[{"award-number":["EP\/H005633,EP\/K008528"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,12,5]]},"DOI":"10.1145\/2830772.2830775","type":"proceedings-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T13:38:13Z","timestamp":1452519493000},"page":"635-646","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":35,"title":["An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors"],"prefix":"10.1145","author":[{"given":"Kathryn E.","family":"Gray","sequence":"first","affiliation":[{"name":"University of Cambridge"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriel","family":"Kerneis","sequence":"additional","affiliation":[{"name":"University of Cambridge"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dominic","family":"Mulligan","sequence":"additional","affiliation":[{"name":"University of Cambridge"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christopher","family":"Pulte","sequence":"additional","affiliation":[{"name":"University of Cambridge"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Susmit","family":"Sarkar","sequence":"additional","affiliation":[{"name":"University of St Andrews"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Sewell","sequence":"additional","affiliation":[{"name":"University of Cambridge"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_2_1","volume-title":"ATEC '05","author":"Bellard F."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993520"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254102"},{"key":"e_1_3_2_1_5_1","unstructured":"J. Alglave and L. Maranget \"The diy tool.\" http:\/\/diy.inria.fr\/.  J. Alglave and L. Maranget \"The diy tool.\" http:\/\/diy.inria.fr\/."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/1987389.1987395"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1926385.1926394"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2103656.2103717"},{"key":"e_1_3_2_1_9_1","article-title":"Validating memory barriers and atomic instructions","author":"McKenney P.","year":"2011","journal-title":"Linux Weekly News"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2594291.2594347"},{"key":"e_1_3_2_1_11_1","first-page":"434","volume-title":"ISCA '86","author":"Dubois M."},{"key":"e_1_3_2_1_12_1","volume-title":"Inc.","author":"Collier W.","year":"1992"},{"key":"e_1_3_2_1_13_1","unstructured":"K. Gharachorloo \"Memory consistency models for shared-memory multiprocessors \"WRL Research Report vol. 95 no. 9 1995.  K. Gharachorloo \"Memory consistency models for shared-memory multiprocessors \" WRL Research Report vol. 95 no. 9 1995."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/40.372352"},{"key":"e_1_3_2_1_15_1","volume-title":"USA: Morgan Kaufmann Publishers Inc.","author":"May C.","year":"1994"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.546611"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2003.1199067"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_25"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.38"},{"key":"e_1_3_2_1_20_1","unstructured":"Power ISA Version 2.06B. IBM 2010. https:\/\/www.power.org\/wp-content\/uploads\/2012\/07\/PowerISA_V2.06B_V2_PUBLIC.pdf (accessed 2015\/07\/22). Power ISA Version 2.06B . IBM 2010. https:\/\/www.power.org\/wp-content\/uploads\/2012\/07\/PowerISA_V2.06B_V2_PUBLIC.pdf (accessed 2015\/07\/22)."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2628136.2628143"},{"key":"e_1_3_2_1_22_1","volume-title":"Processor Description Languages. Morgan Kaufmann","author":"Misra P.","year":"2008"},{"key":"e_1_3_2_1_23_1","first-page":"338","volume-title":"Third International Conference, ITP 2012, Princeton, NJ, USA, August 13-15, 2012. Proceedings (L. Beringer and A. P. Felty, eds.)","volume":"7406","author":"Fox A. C. J.","year":"2012"},{"key":"e_1_3_2_1_24_1","first-page":"91","volume-title":"FMCAD '14","author":"Goel S.","year":"2014"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-25379-9_25"},{"key":"e_1_3_2_1_26_1","first-page":"629","article-title":"Floating-point verification","volume":"13","author":"Harrison J.","year":"2007","journal-title":"Journal of Universal Computer Science"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2011.40"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.40"},{"key":"e_1_3_2_1_29_1","unstructured":"L. Maranget etal \"herdtools.\" https:\/\/github.com\/herd\/herdtools.  L. Maranget et al. \"herdtools.\" https:\/\/github.com\/herd\/herdtools."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/309847.309911"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2837614.2837615"}],"event":{"name":"MICRO-48: The 48th Annual IEEE\/ACM International Symposium of Microarchitecture","location":"Waikiki Hawaii","acronym":"MICRO-48","sponsor":["IEEE Computer Society TC-uARCH","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 48th International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830775","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830775","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:39Z","timestamp":1750225719000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830775"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12,5]]},"references-count":31,"alternative-id":["10.1145\/2830772.2830775","10.1145\/2830772"],"URL":"https:\/\/doi.org\/10.1145\/2830772.2830775","relation":{},"subject":[],"published":{"date-parts":[[2015,12,5]]},"assertion":[{"value":"2015-12-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}