{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:37:58Z","timestamp":1780357078007,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,12,5]],"date-time":"2015-12-05T00:00:00Z","timestamp":1449273600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,12,5]]},"DOI":"10.1145\/2830772.2830785","type":"proceedings-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T13:38:13Z","timestamp":1452519493000},"page":"166-177","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":42,"title":["Confluence"],"prefix":"10.1145","author":[{"given":"Cansu","family":"Kaynak","sequence":"first","affiliation":[{"name":"EcoCloud, EPFL"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Boris","family":"Grot","sequence":"additional","affiliation":[{"name":"University of Edinburgh"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Babak","family":"Falsafi","sequence":"additional","affiliation":[{"name":"EcoCloud, EPFL"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2015,12,5]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"266","article-title":"DBMSs on a modern processor: Where does time go?","author":"Ailamaki A.","year":"1999","unstructured":"A. Ailamaki , D. J. DeWitt , M. D. Hill , and D. A. Wood , \" DBMSs on a modern processor: Where does time go? \" in The VLDB Journal , Sep. 1999 , pp. 266 -- 277 . A. Ailamaki, D. J. DeWitt, M. D. Hill, and D. A. Wood, \"DBMSs on a modern processor: Where does time go?\" in The VLDB Journal, Sep. 1999, pp. 266--277.","journal-title":"The VLDB Journal"},{"key":"e_1_3_2_1_2_1","unstructured":"ARM Processor Technology Update www.arm.com.  ARM Processor Technology Update www.arm.com."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522308"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/123465.123473"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508281"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346301"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.23"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/223982.224439"},{"key":"e_1_3_2_1_9_1","unstructured":"Cavium ThunderX ARM Processors www.cavium.com.  Cavium ThunderX ARM Processors www.cavium.com."},{"key":"e_1_3_2_1_10_1","volume-title":"Context look ahead storage structures","author":"Emma P.","year":"2008","unstructured":"P. Emma , A. Hartstein , B. Prasky , T. Puzak , M. Qureshi , and V. Srinivasan , \" Context look ahead storage structures ,\" Feb. 26 2008 , IBM, US Patent 7,337,271. P. Emma, A. Hartstein, B. Prasky, T. Puzak, M. Qureshi, and V. Srinivasan, \"Context look ahead storage structures,\" Feb. 26 2008, IBM, US Patent 7,337,271."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_1_12_1","volume-title":"Partial resolution in branch target buffers,\" in Proceedings of the Annual International Symposium on Microarchitecture","author":"Fagin B.","year":"1995","unstructured":"B. Fagin and K. Russell , \" Partial resolution in branch target buffers,\" in Proceedings of the Annual International Symposium on Microarchitecture , 1995 . B. Fagin and K. Russell, \"Partial resolution in branch target buffers,\" in Proceedings of the Annual International Symposium on Microarchitecture, 1995."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155638"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771774"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.77"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555779"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.434.0579"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/360128.360137"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540732"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/279358.279364"},{"key":"e_1_3_2_1_23_1","volume-title":"A cost-effective branch target buffer with a two-level table organization,\" in Proceedings of the International Symposium of Low-Power and High-Speed Chips","author":"Kobayashi R.","year":"1999","unstructured":"R. Kobayashi , Y. Yamada , H. Ando , and T. Shimada , \" A cost-effective branch target buffer with a two-level table organization,\" in Proceedings of the International Symposium of Low-Power and High-Speed Chips , 1999 . R. Kobayashi, Y. Yamada, H. Ando, and T. Shimada, \"A cost-effective branch target buffer with a two-level table organization,\" in Proceedings of the International Symposium of Low-Power and High-Speed Chips, 1999."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540731"},{"issue":"5","key":"e_1_3_2_1_25_1","first-page":"12","article-title":"Silvermont energizes Atom","volume":"27","author":"Krewell K.","year":"2013","unstructured":"K. Krewell and L. Gwennap , \" Silvermont energizes Atom ,\" Microprocessor Report , vol. 27 , no. 5 , pp. 12 -- 17 , May 2013 . K. Krewell and L. Gwennap, \"Silvermont energizes Atom,\" Microprocessor Report, vol. 27, no. 5, pp. 12--17, May 2013.","journal-title":"Microprocessor Report"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1984.1658927"},{"key":"e_1_3_2_1_27_1","volume-title":"Scale-out processors,\" in Proceedings of the International Symposium on Computer Architecture","author":"Lotfi-Kamran P.","year":"2012","unstructured":"P. Lotfi-Kamran , B. Grot , M. Ferdman , S. Volos , O. Kocberber , J. Picorel , A. Adileh , D. Jevdjic , S. Idgunji , E. Ozer , and B. Falsafi , \" Scale-out processors,\" in Proceedings of the International Symposium on Computer Architecture , 2012 . P. Lotfi-Kamran, B. Grot, M. Ferdman, S. Volos, O. Kocberber, J. Picorel, A. Adileh, D. Jevdjic, S. Idgunji, E. Ozer, and B. Falsafi, \"Scale-out processors,\" in Proceedings of the International Symposium on Computer Architecture, 2012."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.30"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.214687"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291067"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300999"},{"key":"e_1_3_2_1_32_1","volume-title":"Fetch directed instruction prefetching,\" in Proceedings of the Annual ACM\/IEEE International Symposium on Microarchitecture","author":"Reinman G.","year":"1999","unstructured":"G. Reinman , B. Calder , and T. Austin , \" Fetch directed instruction prefetching,\" in Proceedings of the Annual ACM\/IEEE International Symposium on Microarchitecture , 1999 . G. Reinman, B. Calder, and T. Austin, \"Fetch directed instruction prefetching,\" in Proceedings of the Annual ACM\/IEEE International Symposium on Microarchitecture, 1999."},{"key":"e_1_3_2_1_33_1","volume-title":"Design tradeoffs for the Alpha EV8 conditional branch predictor,\" in Proceedings of the Annual International Symposium on Computer Architecture","author":"Seznec A.","year":"2002","unstructured":"A. Seznec , S. Felix , V. Krishnan , and Y. Sazeides , \" Design tradeoffs for the Alpha EV8 conditional branch predictor,\" in Proceedings of the Annual International Symposium on Computer Architecture , 2002 . A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides, \"Design tradeoffs for the Alpha EV8 conditional branch predictor,\" in Proceedings of the Annual International Symposium on Computer Architecture, 2002."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.1"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2127330"},{"key":"e_1_3_2_1_36_1","unstructured":"E. Sussenguth \"Instruction sequence control \" Jan. 26 1971 US Patent 3 559 183.  E. Sussenguth \"Instruction sequence control \" Jan. 26 1971 US Patent 3 559 183."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.79"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859629"},{"key":"e_1_3_2_1_39_1","volume-title":"A comprehensive instruction fetch mechanism for a processor supporting speculative execution,\" in Proceedings of the Annual International Symposium on Microarchitecture","author":"Yeh T.-Y.","year":"1992","unstructured":"T.-Y. Yeh and Y. N. Patt , \" A comprehensive instruction fetch mechanism for a processor supporting speculative execution,\" in Proceedings of the Annual International Symposium on Microarchitecture , 1992 . T.-Y. Yeh and Y. N. Patt, \"A comprehensive instruction fetch mechanism for a processor supporting speculative execution,\" in Proceedings of the Annual International Symposium on Microarchitecture, 1992."}],"event":{"name":"MICRO-48: The 48th Annual IEEE\/ACM International Symposium of Microarchitecture","location":"Waikiki Hawaii","acronym":"MICRO-48","sponsor":["IEEE Computer Society TC-uARCH","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 48th International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830785","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830785","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:39Z","timestamp":1750225719000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830785"}},"subtitle":["unified instruction supply for scale-out servers"],"short-title":[],"issued":{"date-parts":[[2015,12,5]]},"references-count":39,"alternative-id":["10.1145\/2830772.2830785","10.1145\/2830772"],"URL":"https:\/\/doi.org\/10.1145\/2830772.2830785","relation":{},"subject":[],"published":{"date-parts":[[2015,12,5]]},"assertion":[{"value":"2015-12-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}