{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,24]],"date-time":"2025-12-24T12:15:14Z","timestamp":1766578514657,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":72,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,12,5]],"date-time":"2015-12-05T00:00:00Z","timestamp":1449273600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,12,5]]},"DOI":"10.1145\/2830772.2830804","type":"proceedings-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T13:38:13Z","timestamp":1452519493000},"page":"572-584","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Modeling the implications of DRAM failures and protection techniques on datacenter TCO"],"prefix":"10.1145","author":[{"given":"Panagiota","family":"Nikolaou","sequence":"first","affiliation":[{"name":"University of Cyprus"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiannakis","family":"Sazeides","sequence":"additional","affiliation":[{"name":"University of Cyprus"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lorena","family":"Ndreu","sequence":"additional","affiliation":[{"name":"University of Cyprus"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marios","family":"Kleanthous","sequence":"additional","affiliation":[{"name":"MAP S. Platis"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,5]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"J. Hamilton \"Architecture for modular data centers \" arXiv preprint cs\/0612110 2006. J. Hamilton \"Architecture for modular data centers \" arXiv preprint cs\/0612110 2006."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"L. A. Barroso J. Clidaras and U. H\u00f6lzle \"The datacenter as a computer: An introduction to the design of warehouse-scale machines \" Synthesis lectures on Computer Architecture pp. 1--154 2013. L. A. Barroso J. Clidaras and U. H\u00f6lzle \"The datacenter as a computer: An introduction to the design of warehouse-scale machines \" Synthesis lectures on Computer Architecture pp. 1--154 2013.","DOI":"10.2200\/S00516ED2V01Y201306CAC024"},{"journal-title":"\"Understanding failures in petascale computers,\" Journal of Physics: Conference Series","year":"2007","author":"Schroeder B.","key":"e_1_3_2_1_3_1"},{"volume-title":"Workshop on HPC Resilience at Extreme Scale,\"","year":"2012","author":"Daly J.","key":"e_1_3_2_1_4_1"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/4236.939450"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2009.4"},{"key":"e_1_3_2_1_7_1","first-page":"1","volume-title":"Storage and Analysis","author":"Sridharan V.","year":"2012"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2492101.1555372"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"L. Borucki G. Schindlbeck and C. Slayman \"Comparison of accelerated dram soft error rates measured at component and system level \" in International Reliability Physics Symposium pp. 482--487 April 2008. L. Borucki G. Schindlbeck and C. Slayman \"Comparison of accelerated dram soft error rates measured at component and system level \" in International Reliability Physics Symposium pp. 482--487 April 2008.","DOI":"10.1109\/RELPHY.2008.4558933"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555789"},{"key":"e_1_3_2_1_11_1","unstructured":"G. Daniel Bowers \"Server trends \" TR 2012. G. Daniel Bowers \"Server trends \" TR 2012."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"R. W. Hamming \"Error detecting and error correcting codes \" Bell System Technical Journal pp. 147--160 1950. R. W. Hamming \"Error detecting and error correcting codes \" Bell System Technical Journal pp. 147--160 1950.","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"e_1_3_2_1_13_1","unstructured":"T. J. Dell \"A white paper on the benefits of chipkill-correct ecc for pc server main memory \" IBM Microelectronics Division pp. 1--23 1997. T. J. Dell \"A white paper on the benefits of chipkill-correct ecc for pc server main memory \" IBM Microelectronics Division pp. 1--23 1997."},{"key":"e_1_3_2_1_14_1","unstructured":"S. Ankireddi and T. Chen \"Configuring and using DDR3 memory with HP ProLiant Gen8 Servers Best Practice Guidelines for ProLiant servers with Intel Xeon processors \" February 2014. S. Ankireddi and T. Chen \"Configuring and using DDR3 memory with HP ProLiant Gen8 Servers Best Practice Guidelines for ProLiant servers with Intel Xeon processors \" February 2014."},{"key":"e_1_3_2_1_15_1","unstructured":"\"BIOS and Kernel Developers Guide (BKDG) for AMD Family 15h \" February 2014. \"BIOS and Kernel Developers Guide (BKDG) for AMD Family 15h \" February 2014."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.50"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"C. Constantinescu \"Impact of deep submicron technology on dependability of vlsi circuits \" in International Conference on Dependable Systems and Networks pp. 205--209 2002. C. Constantinescu \"Impact of deep submicron technology on dependability of vlsi circuits \" in International Conference on Dependable Systems and Networks pp. 205--209 2002.","DOI":"10.1109\/DSN.2002.1028901"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"C. Weaver J. Emer S. Mukherjee and S. Reinhardt \"Techniques to reduce the soft error rate of a high-performance microprocessor \" in 31st Annual International Symposium on Computer Architecture pp. 264--275 June 2004. C. Weaver J. Emer S. Mukherjee and S. Reinhardt \"Techniques to reduce the soft error rate of a high-performance microprocessor \" in 31st Annual International Symposium on Computer Architecture pp. 264--275 June 2004.","DOI":"10.1145\/1028176.1006723"},{"key":"e_1_3_2_1_19_1","unstructured":"S. S. Mukherjee C. Weaver J. Emer S. K. Reinhardt and T. Austin \"A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor \" in 36th Annual International Symposium on Microarchitecture 2003. S. S. Mukherjee C. Weaver J. Emer S. K. Reinhardt and T. Austin \"A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor \" in 36th Annual International Symposium on Microarchitecture 2003."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"e_1_3_2_1_21_1","unstructured":"S. Ankireddi and T. Chen \"Challenges in thermal management of memory modules \" Electronics Cooling February 2008. S. Ankireddi and T. Chen \"Challenges in thermal management of memory modules \" Electronics Cooling February 2008."},{"key":"e_1_3_2_1_22_1","unstructured":"\"BIOS and Kernel Developers Guide (BKDG) for AMD Family 10h \" April 2010. \"BIOS and Kernel Developers Guide (BKDG) for AMD Family 10h \" April 2010."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654102"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503243"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"A. N. Udipi N. Muralimanohar R. Balsubramonian A. Davis and N. P. Jouppi \"Lot-ecc: Localized and tiered reliability mechanisms for commodity memory systems \" in 39th Annual International Symposium on Computer Architecture pp. 285--296 2012. A. N. Udipi N. Muralimanohar R. Balsubramonian A. Davis and N. P. Jouppi \"Lot-ecc: Localized and tiered reliability mechanisms for commodity memory systems \" in 39th Annual International Symposium on Computer Architecture pp. 285--296 2012.","DOI":"10.1109\/ISCA.2012.6237025"},{"key":"e_1_3_2_1_26_1","unstructured":"\"Micron 2gb: x4 x8 x16 ddr3 sdram \" Datasheed:https:\/\/www.micron.com\/products\/datasheets. \"Micron 2gb: x4 x8 x16 ddr3 sdram \" Datasheed:https:\/\/www.micron.com\/products\/datasheets."},{"key":"e_1_3_2_1_27_1","unstructured":"\"Intel Xeon Processor E7 Family:Reliability Availability and Serviceability Advanced data integrity and resiliency support for mission-critical deployments \" June 2006. \"Intel Xeon Processor E7 Family:Reliability Availability and Serviceability Advanced data integrity and resiliency support for mission-critical deployments \" June 2006."},{"key":"e_1_3_2_1_28_1","unstructured":"A. Kleen \"mcelog: memory error handling in user space linux \" TR 2010. A. Kleen \"mcelog: memory error handling in user space linux \" TR 2010."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.13"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000103"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196112"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155650"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485974"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"crossref","unstructured":"D. Hardy M. Kleanthous I. Sideris A. Saidi E. Ozer and Y. Sazeides \"An analytical framework for estimating tco and exploring data center design space \" in International Symposium on Performance Analysis of Systems and Software pp. 54--63 2013. D. Hardy M. Kleanthous I. Sideris A. Saidi E. Ozer and Y. Sazeides \"An analytical framework for estimating tco and exploring data center design space \" in International Symposium on Performance Analysis of Systems and Software pp. 54--63 2013.","DOI":"10.1109\/ISPASS.2013.6557146"},{"key":"e_1_3_2_1_35_1","unstructured":"C. Patel and A. Shah \"Cost model for planning development and operation of a data center \" HP TR 2005. C. Patel and A. Shah \"Cost model for planning development and operation of a data center \" HP TR 2005."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/1531743.1531773"},{"key":"e_1_3_2_1_37_1","unstructured":"J. Moore J. Chase P. Ranganathan and R. Sharma \"Making scheduling \"cool\": temperature-aware workload placement in data centers \" in Annual Conference on USENIX pp. 5--5 2005. J. Moore J. Chase P. Ranganathan and R. Sharma \"Making scheduling \"cool\": temperature-aware workload placement in data centers \" in Annual Conference on USENIX pp. 5--5 2005."},{"volume-title":"Uptime Institute","year":"2007","author":"Koomey J.","key":"e_1_3_2_1_38_1"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/1552272.1552275"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063445"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736064"},{"key":"e_1_3_2_1_42_1","unstructured":"\"Hp rom-based setup utility user guide \" February HP TR 2014. \"Hp rom-based setup utility user guide \" February HP TR 2014."},{"volume-title":"TR, 2010.","key":"e_1_3_2_1_43_1"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541258"},{"key":"e_1_3_2_1_45_1","unstructured":"\"HP iLO 3 User Guide \" 2014. http:\/\/h20628.www2.hp.com\/km-ext\/kmcsdirect\/emr_na-c02774507-6.pdf. \"HP iLO 3 User Guide \" 2014. http:\/\/h20628.www2.hp.com\/km-ext\/kmcsdirect\/emr_na-c02774507-6.pdf."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"crossref","unstructured":"A. Sridhar A. Vincenzi M. Ruggiero T. Brunschwiler and D. Atienza \"3d-ice: Fast compact transient thermal modeling for 3d ics with inter-tier liquid cooling \" in International Conference on Computer-Aided Design pp. 463--470 Nov 2010. A. Sridhar A. Vincenzi M. Ruggiero T. Brunschwiler and D. Atienza \"3d-ice: Fast compact transient thermal modeling for 3d ics with inter-tier liquid cooling \" in International Conference on Computer-Aided Design pp. 463--470 Nov 2010.","DOI":"10.1109\/ICCAD.2010.5653749"},{"key":"e_1_3_2_1_47_1","unstructured":"\"lm-sensors \" http:\/\/www.lm-sensors.org\/wiki\/man\/sensors-detect. \"lm-sensors \" http:\/\/www.lm-sensors.org\/wiki\/man\/sensors-detect."},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503257"},{"key":"e_1_3_2_1_49_1","unstructured":"I. Cecil Ho CST \"Innovative testing puts fallout dram back into systems \" January 2003. Simmtester.com. I. Cecil Ho CST \"Innovative testing puts fallout dram back into systems \" January 2003. Simmtester.com."},{"key":"e_1_3_2_1_50_1","unstructured":"\"Memory Test Background \" 2000. http:\/\/tinyurl.com\/m7c3wf7. \"Memory Test Background \" 2000. http:\/\/tinyurl.com\/m7c3wf7."},{"volume-title":"Delft","year":"2005","author":"Al-Ars Z.","key":"e_1_3_2_1_51_1"},{"key":"e_1_3_2_1_52_1","unstructured":"\"Arrhenius equation \" https:\/\/en.wikipedia.org\/wiki\/Arrhenius_equation. \"Arrhenius equation \" https:\/\/en.wikipedia.org\/wiki\/Arrhenius_equation."},{"key":"e_1_3_2_1_53_1","unstructured":"\"Intel Xeon Processor E5620-cost \" http:\/\/www.cpubenchmark.net\/cpu.php?cpu=Intel+Xeon+E5620+%40+2.40GHz. \"Intel Xeon Processor E5620-cost \" http:\/\/www.cpubenchmark.net\/cpu.php?cpu=Intel+Xeon+E5620+%40+2.40GHz."},{"key":"e_1_3_2_1_54_1","unstructured":"\"Desktop Drive 500GB-cost and power \" http:\/\/www.ebuyer.com\/394432-wd-500gb-black-desktop-drive-wd5003azex. \"Desktop Drive 500GB-cost and power \" http:\/\/www.ebuyer.com\/394432-wd-500gb-black-desktop-drive-wd5003azex."},{"key":"e_1_3_2_1_55_1","unstructured":"\"Intel Server Motherboard cost \" http:\/\/www.cpusolutions.com\/store\/pc\/Intel-S1200V3RPS-Server-Motherboard-Intel-C222-Chipset-Socket\/-H3-LGA-1150-p3673.htm#.U4OhLHZqOPM. \"Intel Server Motherboard cost \" http:\/\/www.cpusolutions.com\/store\/pc\/Intel-S1200V3RPS-Server-Motherboard-Intel-C222-Chipset-Socket\/-H3-LGA-1150-p3673.htm#.U4OhLHZqOPM."},{"key":"e_1_3_2_1_56_1","unstructured":"\"Intel cpu configuration \" http:\/\/www.rect.coreto-europe.com\/rack-server\/1u-intel-server\/2428-short-1u-intel-single-cpu-rack-server.html. \"Intel cpu configuration \" http:\/\/www.rect.coreto-europe.com\/rack-server\/1u-intel-server\/2428-short-1u-intel-single-cpu-rack-server.html."},{"key":"e_1_3_2_1_57_1","unstructured":"\"Server cace and power supply \" http:\/\/www.newegg.com\/Product\/Product.aspx?Item=N82E16811108235. \"Server cace and power supply \" http:\/\/www.newegg.com\/Product\/Product.aspx?Item=N82E16811108235."},{"key":"e_1_3_2_1_58_1","unstructured":"\"Kingston Technology ValueRAM 8GB-x4 1600MHz DDR3-cost \" http:\/\/www.amazon.com\/Kingston-Technology-PC3-12800-KVR16LR11S4-8HA\/dp\/B00BYO7CZM. \"Kingston Technology ValueRAM 8GB-x4 1600MHz DDR3-cost \" http:\/\/www.amazon.com\/Kingston-Technology-PC3-12800-KVR16LR11S4-8HA\/dp\/B00BYO7CZM."},{"key":"e_1_3_2_1_59_1","unstructured":"\"Kingston ValueRam 8GB-x8 1600 MHz DDR3-cost \" http:\/\/www.amazon.com\/Kingston-Technology-Validated-KVR16LR11D8-8I\/dp\/B00JWFMBIS. \"Kingston ValueRam 8GB-x8 1600 MHz DDR3-cost \" http:\/\/www.amazon.com\/Kingston-Technology-Validated-KVR16LR11D8-8I\/dp\/B00JWFMBIS."},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541941"},{"key":"e_1_3_2_1_61_1","unstructured":"\"The International Technology Roadmap for Semiconductors ITRS Tech. Rep. \" 2013. http:\/\/www.itrs.ne. \"The International Technology Roadmap for Semiconductors ITRS Tech. Rep. \" 2013. http:\/\/www.itrs.ne."},{"key":"e_1_3_2_1_62_1","unstructured":"\"Hp advanced memory error detection technology \" July TR 2011. \"Hp advanced memory error detection technology \" July TR 2011."},{"edition":"2","volume-title":"\"Hp proliant dl380 g7 server user guide","year":"2011","key":"e_1_3_2_1_63_1"},{"key":"e_1_3_2_1_64_1","unstructured":"\"Cloudsuite web search site \" http:\/\/parsa.epfl.ch\/cloudsuite\/search.html. \"Cloudsuite web search site \" http:\/\/parsa.epfl.ch\/cloudsuite\/search.html."},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_66_1","unstructured":"\"Standard performance evaluation corporation. spec cpu 2006 \" 2006. http:\/\/www.spec.org\/cpu2006\/. \"Standard performance evaluation corporation. spec cpu 2006 \" 2006. http:\/\/www.spec.org\/cpu2006\/."},{"key":"e_1_3_2_1_67_1","unstructured":"\"Prime95 \" http:\/\/www.mersenne.org\/download\/. \"Prime95 \" http:\/\/www.mersenne.org\/download\/."},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"crossref","unstructured":"J. Srinivasan S. V. Adve P. Bose S. V. A. P. Bose and J. A. Rivers \"The case for lifetime reliability-aware microprocessors \" in 31st International Symposium on Computer Architecture pp. 276--287 2004. J. Srinivasan S. V. Adve P. Bose S. V. A. P. Bose and J. A. Rivers \"The case for lifetime reliability-aware microprocessors \" in 31st International Symposium on Computer Architecture pp. 276--287 2004.","DOI":"10.1145\/1028176.1006725"},{"key":"e_1_3_2_1_69_1","unstructured":"K. Bergman S. Borkar D. Campbell W. Carlson W. Dally M. Denneau P. Franzon W. Harrod K. Hill and J. Hiller \"Exascale computing study: Technology challenges in achieving exascale systems \" TR 2008. K. Bergman S. Borkar D. Campbell W. Carlson W. Dally M. Denneau P. Franzon W. Harrod K. Hill and J. Hiller \"Exascale computing study: Technology challenges in achieving exascale systems \" TR 2008."},{"key":"e_1_3_2_1_70_1","unstructured":"\"Intel Xeon Processor E3-power \" http:\/\/www.servethehome.com\/intel-xeon-e3-1220-v3-benchmark-review-haswell-xeon\/. \"Intel Xeon Processor E3-power \" http:\/\/www.servethehome.com\/intel-xeon-e3-1220-v3-benchmark-review-haswell-xeon\/."},{"key":"e_1_3_2_1_71_1","unstructured":"J. Hamilton \"Overall data center costs.\" http:\/\/perspectives.mvdirona.com\/2010\/09\/18\/OverallDataCenterCosts.aspxn. J. Hamilton \"Overall data center costs.\" http:\/\/perspectives.mvdirona.com\/2010\/09\/18\/OverallDataCenterCosts.aspxn."},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150990"}],"event":{"name":"MICRO-48: The 48th Annual IEEE\/ACM International Symposium of Microarchitecture","sponsor":["IEEE Computer Society TC-uARCH","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Waikiki Hawaii","acronym":"MICRO-48"},"container-title":["Proceedings of the 48th International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830804","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830804","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:40Z","timestamp":1750225720000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830804"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12,5]]},"references-count":72,"alternative-id":["10.1145\/2830772.2830804","10.1145\/2830772"],"URL":"https:\/\/doi.org\/10.1145\/2830772.2830804","relation":{},"subject":[],"published":{"date-parts":[[2015,12,5]]},"assertion":[{"value":"2015-12-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}