{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:38:53Z","timestamp":1772725133322,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":38,"publisher":"ACM","license":[{"start":{"date-parts":[[2015,12,5]],"date-time":"2015-12-05T00:00:00Z","timestamp":1449273600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2015,12,5]]},"DOI":"10.1145\/2830772.2830812","type":"proceedings-article","created":{"date-parts":[[2016,1,11]],"date-time":"2016-01-11T13:38:13Z","timestamp":1452519493000},"page":"358-369","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":27,"title":["Filtered runahead execution with a runahead buffer"],"prefix":"10.1145","author":[{"given":"Milad","family":"Hashemi","sequence":"first","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yale N.","family":"Patt","sequence":"additional","affiliation":[{"name":"The University of Texas at Austin"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2015,12,5]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"\"NVIDIA Tegra 4 Family CPU Architecture \" http:\/\/www.nvidia.com\/docs\/IO\/116757\/NVIDIA_Quad_a15_whitepaper_FINALv2.pdf 2013 {Online; Page 13; Accessed 8-May-2015}.  \"NVIDIA Tegra 4 Family CPU Architecture \" http:\/\/www.nvidia.com\/docs\/IO\/116757\/NVIDIA_Quad_a15_whitepaper_FINALv2.pdf 2013 {Online; Page 13; Accessed 8-May-2015}."},{"key":"e_1_3_2_1_2_1","unstructured":"\"Intel 64 and IA-32 Architectures Optimization Reference Manual \" http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/manuals\/64-ia-32-architectures-optimization-manual.pdf 2014 {Online; Page 54; Accessed 4-May-2015}.  \"Intel 64 and IA-32 Architectures Optimization Reference Manual \" http:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/manuals\/64-ia-32-architectures-optimization-manual.pdf 2014 {Online; Page 54; Accessed 4-May-2015}."},{"key":"e_1_3_2_1_3_1","volume-title":"Speculative precomputation on chip multiprocessors,\" in In Proceedings of the 6th Workshop on Multithreaded Execution, Architecture, and Compilation","author":"Brown J. A.","year":"2001","unstructured":"J. A. Brown , H. Wang , G. Chrysos , P. H. Wang , and J. P. Shen , \" Speculative precomputation on chip multiprocessors,\" in In Proceedings of the 6th Workshop on Multithreaded Execution, Architecture, and Compilation , 2001 . J. A. Brown, H. Wang, G. Chrysos, P. H. Wang, and J. P. Shen, \"Speculative precomputation on chip multiprocessors,\" in In Proceedings of the 6th Workshop on Multithreaded Execution, Architecture, and Compilation, 2001."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300995"},{"key":"e_1_3_2_1_6_1","volume-title":"Dynamic speculative precomputation,\" in MICRO-34","author":"Collins J. D.","year":"2001","unstructured":"J. D. Collins , D. M. Tullsen , H. Wang , and J. P. Shen , \" Dynamic speculative precomputation,\" in MICRO-34 , 2001 . J. D. Collins, D. M. Tullsen, H. Wang, and J. P. Shen, \"Dynamic speculative precomputation,\" in MICRO-34, 2001."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379248"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605427"},{"key":"e_1_3_2_1_9_1","unstructured":"Cray Research Inc. \"Cray-1 computer systems hardware reference manual 2240004 \" 1977.  Cray Research Inc. \"Cray-1 computer systems hardware reference manual 2240004 \" 1977."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263597"},{"issue":"2","key":"e_1_3_2_1_11_1","first-page":"696","article-title":"Buffer block prefetching method","volume":"20","author":"Gindele J. D.","year":"1977","unstructured":"J. D. Gindele , \" Buffer block prefetching method ,\" IBM Technical Disclosure Bulletin , vol. 20 , no. 2 , pp. 696 -- 697 , Jul. 1977 . J. D. Gindele, \"Buffer block prefetching method,\" IBM Technical Disclosure Bulletin, vol. 20, no. 2, pp. 696--697, Jul. 1977.","journal-title":"IBM Technical Disclosure Bulletin"},{"key":"e_1_3_2_1_12_1","volume-title":"Bolt: Energy-efficient out-of-order latency-tolerant execution,\" in HPCA-16","author":"Hilton A.","year":"2010","unstructured":"A. Hilton and A. Roth , \" Bolt: Energy-efficient out-of-order latency-tolerant execution,\" in HPCA-16 , 2010 . A. Hilton and A. Roth, \"Bolt: Energy-efficient out-of-order latency-tolerant execution,\" in HPCA-16, 2010."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264207"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950411"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605415"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379259"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.18"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379250"},{"key":"e_1_3_2_1_21_1","volume-title":"Apr.","author":"Datasheet Rev DRAM","year":"2010","unstructured":"\"MT41J512M4 DDR3 S DRAM Datasheet Rev . K Micron Technology , Apr. 2010 ,,\" http:\/\/download.micron.com\/pdf\/datasheets\/dram\/ddr3\/2Gb_DDR3_SDRAM.pdf. \"MT41J512M4 DDR3 SDRAM Datasheet Rev. K Micron Technology, Apr. 2010,,\" http:\/\/download.micron.com\/pdf\/datasheets\/dram\/ddr3\/2Gb_DDR3_SDRAM.pdf."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054951"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.49"},{"key":"e_1_3_2_1_25_1","volume-title":"Runahead execution: An alternative to very large instruction windows for out-of-order processors,\" in HPCA-9","author":"Mutlu O.","year":"2003","unstructured":"O. Mutlu , J. Stark , C. Wilkerson , and Y. N. Patt , \" Runahead execution: An alternative to very large instruction windows for out-of-order processors,\" in HPCA-9 , 2003 . O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt, \"Runahead execution: An alternative to very large instruction windows for out-of-order processors,\" in HPCA-9, 2003."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10030"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/191995.192014"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/291069.291034"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/605397.605403"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.476078"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024407"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379247"},{"key":"e_1_3_2_1_35_1","volume-title":"Oct.","author":"Tendler J. M.","year":"2001","unstructured":"J. M. Tendler , J. S. Dodson , J. S. Fields , H. Le , and B. Sinharoy , \" POWER4 system microarchitecture,\" IBM Technical White Paper , Oct. 2001 . J. M. Tendler, J. S. Dodson, J. S. Fields, H. Le, and B. Sinharoy, \"POWER4 system microarchitecture,\" IBM Technical White Paper, Oct. 2001."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2370816.2370865"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/373574.373576"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346187"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379246"}],"event":{"name":"MICRO-48: The 48th Annual IEEE\/ACM International Symposium of Microarchitecture","location":"Waikiki Hawaii","acronym":"MICRO-48","sponsor":["IEEE Computer Society TC-uARCH","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["Proceedings of the 48th International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830812","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/2830772.2830812","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T05:48:40Z","timestamp":1750225720000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/2830772.2830812"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12,5]]},"references-count":38,"alternative-id":["10.1145\/2830772.2830812","10.1145\/2830772"],"URL":"https:\/\/doi.org\/10.1145\/2830772.2830812","relation":{},"subject":[],"published":{"date-parts":[[2015,12,5]]},"assertion":[{"value":"2015-12-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}